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mt9m131: 1/3-inch 1.3mp soc digital image sensor features mt9m131 ds rev. h 5/15 en 1 ?semiconductor components industries, llc,2015 1/3-inch soc 1.3 mp cmos digital image sensor mt9m131 datasheet, rev. h for the latest datasheet, please visit www.onsemi.com features ? system-on-a-chip (soc)? completely integrated camera system ? ultra-low power, cost effective, progressive scan cmos image sensor ? superior low-light performance ? on-chip image flow processor (ifp) performs sophisticated processing: ? color recovery and correction ? sharpening, gamma, lens shading correction ? on-the-fly defect correction ? electronic pan, tilt, and zoom ? automatic features: ? auto exposure (ae), auto white balance (awb), auto black reference (abr), auto flicker avoidance, auto color saturation, auto defect identification and correction ? fully automatic xenon and led-type flash sup- port ? fast exposure adaptation ? multiple parameter contexts ? easy and fast mode switching ? camera control sequencer automates: ? snapshots ? snapshots with flash ? video clips ?simple two-wire serial programming interface ? itu-r bt.656 (ycbcr), 565rgb, 555rgb, or 444rgb formats (progressive scan) ? raw and processed bayer formats ? output fifo and integer clock divider: ? uniform pixel clocking applications ?security ?biometrics ? videoconferencing ?toys table 1: key performance parameters parameter value optical format 1/3-inch (5:4) active imager size 4.6 mm (h) x 3.7 mm (v), 5.9mm diagonal active pixels 1280h x 1024v pixel size 3.6 x 3.6 ? m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 27 mps/54 mhz frame rate sxga (1280 x 1024) 15 fps at 54 mhz vga (640 x 480) 30 fps at 54 mhz maximum resolution at 60 fps/54 mhz clock 640 x 512 adc resolution 10-bit, dual on-chip responsivity 1.0 v/lux-sec (550nm) dynamic range 71 db snr max 44 db supply voltage i/o digital 1.8C3.1 v core digital 2.5C3.1 v analog 2.5C3.1 v power consumption 170mw sxga at 15 fps (54 mhz extclk) operating temperature C30c to +70c packaging 48-pin clcc
mt9m131 ds rev. h 5/15 en 2 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9m131c12stc-dp 1.3 mp 1/3" soc dry pack with protective film mt9m131c12stc-dr 1.3 mp 1/3" soc dry pack without protective film MT9M131C12STC-TP 1.3 mp 1/3" soc tape & reel with protective film mt9m131c12stc-tr 1.3 mp 1/3" soc tape & reel without protective film
mt9m131 ds rev. h 5/15 en 3 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 register operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 typical connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 ifp register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 ifp register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 camera control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 sensor core overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 sensor core register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 sensor core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 sensor read modes and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 appendix a ? serial bus description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
mt9m131 ds rev. h 5/15 en 4 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor list of figures list of figures figure 1: functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: internal registers grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: register legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: 48-pin clcc assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 7: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 9: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 10: primary sensor core clock rela tionships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 11: vertical timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 12: horizontal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 13: ac output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 15: cra versus image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 16: optical center diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 17: write timing to r0x 009?value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 18: read timing from r0x0 09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 19: write timing to r0x 009?value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 20: read timing from r0x0 09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 21: two-wire serial interf ace timing diagram at th e pins of the sensor. . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 22: two-wire serial interf ace timing diagram at th e pins of the sensor (2). . . . . . . . . . . . . . . . . . . . . . . . 65 figure 23: 48-pin clcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
mt9m131 ds rev. h 5/15 en 5 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin/ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4: data ordering in ycbcr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: output data ordering in processed bayer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: output data ordering in rgb mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 7: output data ordering in (8 + 2) bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 8: colorpipe registers (address page 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 9: camera control registers (address page 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 10: colorpipe register description address page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 11: camera control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 12: sensor registers (address page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 13: sensor core register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 14: register address functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 15: blanking parameter calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 16: user blanking minimum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 17: blanking definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 18: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 19: i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 20: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 21: power consumption at 2.8v (in mw). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 22: ac output timing data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 23: two-wire serial interf ace timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
mt9m131: 1/3-inch 1.3mp soc digital image sensor general description mt9m131 ds rev. h 5/15 en 6 ?semiconductor components industries, llc,2015. general description the mt9m131 is an sxga-format single-chip ca mera with a 1/3-inch cmos active-pixel digital image sensor. this device combines the mt9m011 image sensor core with fourth-generation digital image flow proces sor technology from on semiconductor. it captures high-quality color images at sxga resolution. the mt9m131 features on semiconductor?s breakthrough low-noise cmos imaging technology that achieves near-ccd image qu ality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advan- tages of cmos. the sensor is a complete camera-on-a-chip so lution designed specifically to meet the demands of products such as security, biometrics, and vi deoconferencing cameras. it incorporates sophisticated camera function s on-chip and is programmable through a simple two-wire serial interface. the mt9m131 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure (ae), automatic 50hz/60hz flicker avoidance, lens shading correction (lc), auto white balance (awb), and on-the-fly defect identification and correction. additional features include day/night mode configurations; special camera effects such as sepia tone and solarization; an d interpolation to arbi trary image size with continuous filtered zoom and pan. the devi ce supports both xenon and led-type flash light sources in several snapshot modes. the mt9m131 can be programmed to output pr ogressive-scan images up to 30 frames per second (fps) in preview power-saving mode, and 15 fps in full-resolution (sxga) mode. in either mode, the image data can be output in any one of six formats: ? itu-r bt.656 (formerly ccir656, progressive scan only) ycbcr ? 565rgb ? 555rgb ? 444rgb ? raw bayer ?processed bayer the fv and lv signals are output on dedicate d signals, along with a pixel clock that is synchronous with valid data.
mt9m131 ds rev. h 5/15 en 7 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor functional overview functional overview the mt9m131 is a fully-automatic, single-chip camera, requiring only a power supply, lens, and clock source for basic operation. ou tput video is streamed through a parallel 8- or 10-bit d out port, shown in figure 1. figure 1: functional block diagram the output pixel clock is used to latch data, while fv and lv signal s indicate the active video. the mt9m131 internal registers are conf igured using a two-wire serial interface. the device can be put in low-power sleep mode by asserting standby and shutting down the clock. output pins can be tri- stated by de-asserting the oe_bar. both tri-stating output pins and entry in standby mode also can be achieved by two-wire serial interface register writes. the mt9m131 accepts input clocks up to 54 mhz, delivering up to 15 fps for sxga reso- lution images, and up to 30 fps for qsxga (f ull field-of-view [fov], sensor pixel skip- ping) images. the device also supports a low- power preview configur ation that delivers sxga images at 7.5 fps and qs xga images at 30 fps. the device can be programmed to slow the frame rate in low light conditions to achieve longer exposures and better image quality. sensor core sram line buffers image flow processor colorpipe image flow processor camera control image data control bus (two-wire serial i/f transactions) pixel data sclk s data extclk standby oe_bar v dd_ io/d gnd io v dd /d gnd v aa /a gnd vaa_pix 1316h x 1048v including black 1/3-inch optical format auto black compensation programmable analog gain programmable exposure dual 10-bit adcs low-power preview mode h/w context switch to/from preview bayer rgb output lens shading correction color interpolation filtered resize and zoom defect correction color correction gamma correction color conversion + formatting output fifo auto exposure auto white balance flicker detect/avoid camera control: snapshots, flash, video, clip control bus (two-wire serial i/f trans.) d out [7:0]: d out_ lsb[1:0] pixclk fv lv strobe control bus (two-wire serial i/f transactions) + sensor control (gains, shutter, etc.)
mt9m131: 1/3-inch 1.3mp soc digital image sensor functional overview mt9m131 ds rev. h 5/15 en 8 ?semiconductor components industries, llc,2015. internal architecture internally, the mt9m131 consists of a sensor core and an ifp. the ifp is divided in two sections: the colorpipe (cp), and the camera controller (cc). the sensor core captures raw bayer-encoded images that are then input in the ifp. the cp section of the ifp processes the incoming stream to create in terpolated, color-corrected output, and the cc section controls the sensor core to main tain the desired exposure and color balance, and to support snapshot modes. the sensor core, cp, and cc registers are grouped in three separate address spaces, as shown in figure 2. figure 2: internal registers grouping notes: 1. internal registers are grouped in three address spaces. register r0xf0 in each page selects the desired address space. when accessing internal registers through the two-wire serial interface, select the desired address space by programming the r0xf0 shared register. the mt9m131 accelerates mode switching with hardware-assisted context switching and supports taking snapshots, flash snapsh ots, and video clips using a configurable sequencer. the mt9m131 supports a range of color formats derived from four primary color repre- sentations: ycbcr, rgb, raw bayer (unpro cessed, directly from the sensor), and processed bayer (bayer format data regenerated from processed rgb). the device also supports a variety of output signaling/timing options: ? standard fv/lv video interface with gated pixel clocks ? standard video interface with uniform clocking ? progressive itu-r bt.656 marker-embedded video interface with either gated or uniform pixel clocking image flow processor sensor core registers r0x000 - r0x0ff r0xf0 = 0 color pipeline registers r0x100 - r0x1ff r0xf0 = 1 camera control registers r0x200 - r0x2ff r0xf0 = 2
mt9m131 ds rev. h 5/15 en 9 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor register operations register operations this data sheet refers to various registers that the user reads from or writes to for altering the mt9m131 operation. hardware registers appear as follows and may be read from or written to by sending the address and data inform ation over the two-wire serial inter- face. figure 3: register legend the mt9m131 was designed to facilitate cu stomizations to opti mize image quality processing. multiple parameters are allowed to be adjusted at various stages of the image processing pipeli ne to tune the quality of the output image. the mt9m131 contains three register pages: sensor, colorpipe, and camera control. the register page must be set prior to writing to a register in the page. for example, to write to register r0x106 (register 6 in page 1): ? write the value of ?1? to the page map register (0xf0) ? write the desired value to register r0x06 the sensor maintains the page number once se t. the page map register is located at address 0xf0 for all three register pages. r0xn24 [4:3] register number [00 to ff] indication of register (as opposed to driver variable) page number (0, 1, or 2) denotes hexadecimal notation register bits [15 to 0]
mt9m131: 1/3-inch 1.3mp soc digital image sensor typical connection mt9m131 ds rev. h 5/15 en 10 ?semiconductor components industries, llc,2015. typical connection figure 4 shows typical mt9m131 device connections. figure 4: typical configuration (connection) notes: 1. for two-wire serial interface, on semiconductor recommends a 1.5k ? resistor; however, larger val- ues may be used for slower two-wire speed. 2. v dd , v aa , vaa_pix must all be at the same potential, though if connected, care must be taken to avoid excessive noise injection in the v aa /vaa_pix power domains. 3. logic levels of all input pins, that is, s addr , extclk, sclk, s data , oe_bar, standby, and reset_bar must be equal to v dd _io. for low-noise operation, the mt9m131 requires separate power supplies for analog and digital. incoming digital and analog ground co nductors can be tied together next to the die. both power supply rails should be decoupled to ground using ceramic capacitors. the use of inductance filters is not recommended. the mt9m131 also supports different digital core (v dd / d gnd ) and i/o power (v dd _io/ d gnd io) power domains that can be at different voltages. 0.1f 0.1f 0.1f 1f master clock powe r -on reset digital gnd analog gnd 1f 1f two-wire serial interface to cmos camera port to xenon or led flash driver sclk s data saddr sclk s data extclk reset_bar oe_bar standby d gnd io d gnd a gnd 1.8v?3.1v i/o digital 2.8v core digital 2.8v analog d out [7:0]:d out lsb[1:0] frame_valid line_valid pixclk strobe 1.5k ? 1.5k ? v dd_ io v dd v aa /vaa_pix d gnd io d gnd a gnd v dd_ io v dd v aa vaa_pix
mt9m131 ds rev. h 5/15 en 11 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor typical connection pin/ball assignment the mt9m131 is available in the clcc packag e configuration. figure 5 shows the 48-pin clcc assignment. figure 5: 48-pin clcc assignment 1 2 3 4 5 648474645 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 d gnd v dd d out [4] d out [5] d out [6] d out [7] d gnd v dd io d out_ lsb0 d out_ lsb1 d gnd v dd nc v dd d gnd s data test_en v dd io d gnd vaapix a gnd a gnd v aa v aa s addr lv fv reset_bar d gnd v dd standby oe_bar strobe d gnd v dd io nc d out [3] d out [2] d out [1] d out [0] v dd d gnd pixclk v dd io d gnd extclk sclk nc
mt9m131: 1/3-inch 1.3mp soc digital image sensor typical connection mt9m131 ds rev. h 5/15 en 12 ?semiconductor components industries, llc,2015. notes: 1. all inputs and outputs are implemented with bi directional buffers. care must be taken to ensure that all inputs are driven and all outputs are driven if tri-stated. table 3: pin/ball descriptions signal type default operation description extclk i/o input master clock in sensor. oe_bar i/o input active low: output enable for d out [7:0]. reset_bar i/o input active low: asynchronous reset. s addr i/o input two-wire serial interface deviceid selection 1:0xba, 0:0x90. sclk i/o input two-wire serial interface clock. standby i/o input active high: disables imager. s data i/o input two-wire serial interface data i/o. test_en i/o input tie to d gnd for normal operation (manufacturing use only). d out 0i/ooutput d out 1i/ooutput d out 2i/ooutput d out 3i/ooutput d out 4i/ooutput d out 5i/ooutput d out 6i/ooutput d out 7i/ooutput d out _lsb0 i/o output sensor bypass mode output 0typically left unconnected for normal soc operation. d out _lsb1 i/o output sensor bypass mode output 1typically left unconnected for normal soc operation. frame_valid(fv ) i/o output active high: fv; indicates active frame. line_valid (lv) i/o output active high: lv, data_valid; indicates active pixel. pixclk i/o output pixel clock output. strobe i/o output active high: strobe (xenon) or turn on (led) flash. a gnd supply analog ground. d gnd supply core digital ground. d gnd io supply i/o digital ground. v aa supply analog power (2.5 ? 3.1v). vaapix supply pixel array analog power supply (2.5 ? 3.1v). v dd supply core digital power (2.5 ? 3.1v). v dd io supply i/o digital power (1.8 ? 3.1v). nc C no connect.
mt9m131 ds rev. h 5/15 en 13 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor output data ordering output data ordering table 4: data ordering in ycbcr mode mode byte default cbi yi cri yi+1 swap crcb cri yi cbi yi+1 swapyc yi cbi yi+1 cri swap crcb, swapyc yi cri yi+1 cbi table 5: output data ordering in processed bayer mode mode line byte default first gi ri+1 gi+2 ri+3 second bi gi+1 bi+2 gi+3 flip bayer col first ri gi+1 ri+2 gi+3 second gi bi+1 gi+2 bi+3 flip bayer row first bi gi+1 bi+2 gi+3 second gi ri+1 gi+2 ri+3 flip bayer col, flip bayer row first gi bi+1 gi+2 bi+3 second ri gi+1 ri+2 gi+3 table 6: output data ordering in rgb mode mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 565rgb firstr7r6r5r4r3g7g6g5 second g4 g3 g2 b7 b6 b5 b4 b3 555rgb first 0 r7 r6 r5 r4 r3 g7 g6 second g5 g4 g3 b7 b6 b5 b4 b3 444xrgb first r7 r6 r5 r4 g7 g6 g5 g4 secondb7b6b5b40000 x444rgb first 0 0 0 0 r7 r6 r5 r4 second g7 g6 g5 g4 b7 b6 b5 b4 table 7: output data ordering in (8 + 2) bypass mode mode byte d7 d6 d5 d4 d3 d2 d1 d0 8 + 2 bypassfirstb9b8b7b6b5b4b3b2 second000000b1b0
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list mt9m131 ds rev. h 5/15 en 14 ?semiconductor components industries, llc,2015. ifp register list table 8: colorpipe registers (address page 1) register number dec (hex) register name data format (binary) default value dec (hex) module r5 (r0x105) aperture correction 0000 0000 0000 dddd 3 (0003) interp r6 (r0x106) operating mode control dddd dddd 0ddd dddd 28686 (700e) cfg r8 (r0x108) output format control 0000 0ddd dddd dddd 128 (0080) cfg r16 (r0x110) reserved C 61437 (effd) C r17 (r0x111) reserved C 64831 (fd3f) C r18 (r0x112) reserved C 16367 (3fef) C r19 (r0x113) reserved C n/a C r20 (r0x114) reserved C n/a C r21 (r0x115) reserved C n/a C r27 (r0x11b) reserved C 0 (0000) C r28 (r0x11c) reserved C 0 (0000) C r29 (r0x11d) reserved C n/a C r30 (r0x11e) reserved C 512 (0200) C r37 (r0x125) color saturation control 0000 0000 00dd dddd 5 (0005) rgb2yuv r52 (r0x134) luma offset dddd dddd dddd dddd 16 (0010) camlnt r53 (r0x135) luma clip dddd dddd dddd dddd 61456 (f010) camlnt r58 (r0x13a) output format control 2context a 0ddd dddd dddd dddd 512 (0200) camint r59 (r0x13b) 1066 (042a) lenscorr r60 (r0x13c) 1024 (0400) lenscorr r71 (r0x147) 24 (0018) r72 (r0x148) test pattern generator control 0000 0000 d000 0ddd 0 (0000) fifoint r76 (r0x14c) defect correction context a 0000 0000 0000 0ddd 0 (0000) dfctcorr r77 (r0x14d) defect correction context b 0000 0000 0000 0ddd 0 (0000) dfctcorr r78 (r0x14e) reserved C 10 (000a) C r80 (r0x150) n/a r82 (r0x152) reserved C 0 (0000) C r83 (r0x153) 7700 (1e14) gmacorr r84 (r0x154) 17966 (462e) gmacorr r85 (r0x155) 34666 (876a) gmacorr r86 (r0x156) 47008 (b7a0) gmacorr r87 (r0x157) 57548 (e0cc) gmacorr r88 (r0x158) 0 (0000) gmacorr r104 (r0x168) reserved C 17 (0011) C r128 (r0x180) 7 (0007) lenscorr r129 (r0x181) 56588 (dd0c) lenscorr r130 (r0x182) 62696 (f4e8) lenscorr r131 (r0x183) 1276 (04fc) lenscorr r132 (r0x184) 57868 (e20c) lenscorr r133 (r0x185) 63212 (f6ec) lenscorr r134 (r0x186) 764 (02fc) lenscorr r135 (r0x187) 56588 (dd0c) lenscorr r136 (r0x188) 62696 (f4e8) lenscorr
mt9m131 ds rev. h 5/15 en 15 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list r137 (r0x189) 250 (00fa) lenscorr r138 (r0x18a) 34866 (8832) lenscorr r139 (r0x18b) 56754 (ddb2) lenscorr r140 (r0x18c) 63466 (f7ea) lenscorr r141 (r0x18d) 2 (0002) lenscorr r142 (r0x18e) 47646 (ba1e) lenscorr r143 (r0x18f) 60627 (ecd3) lenscorr r144 (r0x190) 63473 (f7f1) lenscorr r145 (r0x191) 255 (00ff) lenscorr r146 (r0x192) 48926 (bf1e) lenscorr r147 (r0x193) 61142 (eed6) lenscorr r148 (r0x194) 63474 (f7f2) lenscorr r149 (r0x195) 3 (0003) lenscorr r153 (r0x199) line counter ???? ???? ???? ???? n/a camint r154 (r0x19a) frame counter ???? ???? ???? ???? n/a camint r155 (r0x19b) output format control 2context b 0ddd dddd dddd dddd 512 (0200) camint r157 (r0x19d) reserved C 9390 (24ae) C r158 (r0x19e) reserved C n/a C r159 (r0x19f) reducer horizontal pancontext b 0d00 0ddd dddd dddd 0 (0000) interp r160 (r0x1a0) reducer horizontal zoomcontext b 0000 0ddd dddd dddd 1280 (0500) interp r161 (r0x1a1) reducer horizontal sizecontext b 0000 0ddd dddd dddd 1280 (0500) interp r162 (r0x1a2) reducer vertical pancontext b 0d00 0ddd dddd dddd 0 (0000) interp r163 (r0x1a3) reducer vertical zoomcontext b 0000 0ddd dddd dddd 1024 (0400) interp r164 (r0x1a4) reducer vertical sizecontext b 0000 0ddd dddd dddd 1024 (0400) interp r165 (r0x1a5) reducer horizontal pancontext a 0d00 0ddd dddd dddd 0 (0000) interp r166 (r0x1a6) reducer horizontal zoomcontext a 0000 0ddd dddd dddd 1280 (0500) interp r167 (r0x1a7) reducer horizontal sizecontext a 0000 0ddd dddd dddd 640 (0280) interp r168 (r0x1a8) reducer vertical pancontext a 0d00 0ddd dddd dddd 0 (0000) interp r169 (r0x1a9) reducer vertical zoomcontext a 0000 0ddd dddd dddd 1024 (0400) interp r170 (r0x1aa) reducer vertical sizecontext a 0000 0ddd dddd dddd 512 (0200) interp r171 (r0x1ab) reducer current zoom horizontal ???? 0??? ???? ???? n/a interp r172 (r0x1ac) reducer current zoom ve rtical ???? 0??? ???? ???? n/a interp r174 (r0x1ae) reducer zoom step size dddd dddd dddd dddd 1284 (0504) interp r175 (r0x1af) reducer zoom control 0000 00dd 0ddd dddd 16 (0010) interp r179 (r0x1b3) global clock control 0000 0000 0000 00dd 2 (0002) clockrst r180 (r0x1b4) 32 (0020) r181 (r0x1b5) 257 (0101) r182 (r0x1b6) 4363 (110b) lenscorr r183 (r0x1b7) 15399 (3c27) lenscorr r184 (r0x1b8) 4362 (110a) lenscorr r185 (r0x1b9) 12834 (3222) lenscorr r186 (r0x1ba) 5643 (160b) lenscorr r187 (r0x1bb) 12836 (3224) lenscorr r188 (r0x1bc) 9228 (240c) lenscorr r189 (r0x1bd) 24124 (5e3c) lenscorr table 8: colorpipe registers (address page 1) (continued) register number dec (hex) register name data format (binary) default value dec (hex) module
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list mt9m131 ds rev. h 5/15 en 16 ?semiconductor components industries, llc,2015. r190 (r0x1be) 127 (007f) lenscorr r191 (r0x1bf) 8200 (2008) lenscorr r192 (r0x1c0) 20023 (4e37) lenscorr r193 (r0x1c1) 100 (0064) lenscorr r194 (r0x1c2) 8463 (210f) lenscorr r195 (r0x1c3) 19250 (4b32) lenscorr r196 (r0x1c4) 100 (0064) lenscorr r200 (r0x1c8) global context control dddd dddd dddd dddd 0 (0000) cntxctl r201 (r0x1c9) reserved C n/a C r202 (r0x1ca) reserved C n/a C r203 (r0x1cb) reserved C n/a C r204 (r0x1cc) reserved C n/a C r205 (r0x1cd) reserved C n/a C r206 (r0x1ce) reserved C n/a C r207 (r0x1cf) reserved C n/a C r208 (r0x1d0) reserved C n/a C r220 (r0x1dc) 7700 (1e14) gmacorr r221 (r0x1dd) 17966 (462e) gmacorr r222 (r0x1de) 34666 (876a) gmacorr r223 (r0x1df) 47008 (b7a0) gmacorr r224 (r0x1e0) 57548 (e0cc) gmacorr r225 (r0x1e1) 0 (0000) gmacorr r226 (r0x1e2) effects mode dddd dddd 0000 0ddd 28672 (7000) gmacorr r227 (r0x1e3) effects sepia dddd dddd dddd dddd 45091 (b023) gmacorr r240 (r0x1f0) page map 0000 0000 0000 0ddd 0 (0000) cfg r241 (r0x1f1) byte-wise address C reserved C table 8: colorpipe registers (address page 1) (continued) register number dec (hex) register name data format (binary) default value dec (hex) module
mt9m131 ds rev. h 5/15 en 17 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list table 9: camera control registers (address page 2) register number dec (hex) register name data format (binary) default value dec (hex) module r2 (r0x202) 110 (006e) colorcorr r3 (r0x203) 10531 (2923) colorcorr r4 (r0x204) 1316 (0524) colorcorr r9 (r0x209) 146 (0092) colorcorr r10 (r0x20a) 22 (0016) colorcorr r11 (r0x20b) 8 (0008) colorcorr r12 (r0x20c) 171 (00ab) colorcorr r13 (r0x20d) 147 (0093) colorcorr r14 (r0x20e) 88 (0058) colorcorr r15 (r0x20f) 77 (004d) colorcorr r16 (r0x210) 169 (00a9) colorcorr r17 (r0x211) 160 (00a0) colorcorr r18 (r0x212) n/a colorcorr r19 (r0x213) n/a colorcorr r20 (r0x214) n/a colorcorr r21 (r0x215) 373 (0175) colorcorr r22 (r0x216) 22 (0016) colorcorr r23 (r0x217) 67 (0043) colorcorr r24 (r0x218) 12 (000c) colorcorr r25 (r0x219) 0 (0000) colorcorr r26 (r0x21a) 21 (0015) colorcorr r27 (r0x21b) 31 (001f) colorcorr r28 (r0x21c) 22 (0016) colorcorr r29 (r0x21d) 152 (0098) colorcorr r30 (r0x21e) 76 (004c) colorcorr r31 (r0x21f) 160 (00a0) awb r32 (r0x220) 51220 (c814) awb r33 (r0x221) 32896 (8080) awb r34 (r0x222) 55648 (d960) awb r35 (r0x223) 55648 (d960) awb r36 (r0x224) 32512 (7f00) awb r38 (r0x226) auto exposure window horizontal boundaries dddd dddd dddd dddd 32768 (8000) autoexp r39 (r0x227) auto exposure window vertical bo undaries dddd dddd dddd dddd 32776 (8008) autoexp r40 (r0x228) 61188 (ef04) awb r41 (r0x229) 36211 (8d73) awb r42 (r0x22a) 208 (00d0) awb r43 (r0x22b) auto exposure center horizontal window boundaries dddd dddd dddd dddd 24608 (6020) autoexp r44 (r0x22c) auto exposure center vertical window boundaries dddd dddd dddd dddd 24608 (6020) autoexp r45 (r0x22d) awb window boundaries dddd dddd dddd dddd 61600 (f0a0) awb r46 (r0x22e) auto exposure target and precision control dddd dddd dddd dddd 3146 (0c4a) autoexp r47 (r0x22f) auto exposure speed and sensitivity control context a dddd dddd dddd dddd 57120 (df20) autoexp r48 (r0x230) n/a awb r49 (r0x231) n/a awb r50 (r0x232) n/a awb
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list mt9m131 ds rev. h 5/15 en 18 ?semiconductor components industries, llc,2015. r51 (r0x233) 5230 (146e) autoexp r54 (r0x236) 30736 (7810) autoexp r55 (r0x237) 768 (0300) autoexp r56 (r0x238) 1088 (0440) autoexp r57 (r0x239) 1676 (068c) autoexp r58 (r0x23a) 1676 (068c) autoexp r59 (r0x23b) 1676 (068c) autoexp r60 (r0x23c) 1676 (068c) autoexp r61 (r0x23d) 6105 (17d9) autoexp r62 (r0x23e) 7423 (1cff) awb r63 (r0x23f) n/a autoexp r70 (r0x246) 55552 (d900) autoexp r75 (r0x24b) reserved C 0 (0000) C r76 (r0x24c) n/a autoexp r77 (r0x24d) n/a autoexp r79 (r0x24f) reserved C n/a C r87 (r0x257) 537 (0219) autoexp r88 (r0x258) 644 (0284) autoexp r89 (r0x259) 537 (0219) autoexp r90 (r0x25a) 644 (0284) autoexp r91 (r0x25b) flicker control 0 ?000 0000 0000 0ddd 2 (0002) fd r92 (r0x25c) 4620 (120c) r93 (r0x25d) 5394 (1512) r94 (r0x25e) 26684 (683c) colorcorr r95 (r0x25f) 12296 (3008) colorcorr r96 (r0x260) 2 (0002) colorcorr r97 (r0x261) 32896 (8080) r98 (r0x262) auto exposure digital gains monitor ???? ???? ???? ???? n/a autoexp r99 (r0x263) reserved C n/a C r100 (r0x264) reserved C 23036 (59fc) C r101 (r0x265) 0 (0000) autoexp r103 (r0x267) auto exposure digital gain limits dddd dddd dddd dddd 16400 (4010) autoexp r104 (r0x268) reserved C 17 (0011) C r106 (r0x26a) reserved C n/a C r107 (r0x26b) reserved C n/a C r108 (r0x26c) reserved C n/a C r109 (r0x26d) reserved C n/a C r110 (r0x26e) reserved C n/a C r111 (r0x26f) reserved C n/a C r112 (r0x270) reserved C n/a C r113 (r0x271) reserved C n/a C r114 (r0x272) reserved C n/a C r115 (r0x273) reserved C n/a C r116 (r0x274) reserved C n/a C r117 (r0x275) reserved C n/a C table 9: camera control registers (address page 2) (continued) register number dec (hex) register name data format (binary) default value dec (hex) module
mt9m131 ds rev. h 5/15 en 19 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list r118 (r0x276) reserved C n/a C r119 (r0x277) reserved C n/a C r120 (r0x278) reserved C n/a C r121 (r0x279) reserved C n/a C r122 (r0x27a) reserved C n/a C r123 (r0x27b) reserved C n/a C r124 (r0x27c) reserved C n/a C r125 (r0x27d) reserved C n/a C r130 (r0x282) 1020 (03fc) autoexp r131 (r0x283) 769 (0301) autoexp r132 (r0x284) 193 (00c1) autoexp r133 (r0x285) 929 (03a1) autoexp r134 (r0x286) 980 (03d4) autoexp r135 (r0x287) 983 (03d7) autoexp r136 (r0x288) 921 (0399) autoexp r137 (r0x289) 1016 (03f8) autoexp r138 (r0x28a) 28 (001c) autoexp r139 (r0x28b) 957 (03bd) autoexp r140 (r0x28c) 987 (03db) autoexp r141 (r0x28d) 957 (03bd) autoexp r142 (r0x28e) 1020 (03fc) autoexp r143 (r0x28f) 990 (03de) autoexp r144 (r0x290) 990 (03de) autoexp r145 (r0x291) 990 (03de) autoexp r146 (r0x292) 990 (03de) autoexp r147 (r0x293) 31 (001f) autoexp r148 (r0x294) 65 (0041) autoexp r149 (r0x295) 867 (0363) autoexp r150 (r0x296) reserved C 0 (0000) C r151 (r0x297) reserved C n/a C r152 (r0x298) reserved C 255 (00ff) C r153 (r0x299) reserved C 1 (0001) C r156 (r0x29c) auto exposure sp eed and sensitivity control context b dddd dddd dddd dddd 57120 (df20) autoexp r180 (r0x2b4) reserved C 32 (0020) C r181 (r0x2b5) reserved C n/a C r198 (r0x2c6) reserved C 0 (0000) C r199 (r0x2c7) reserved C n/a C r200 (r0x2c8) global context control dddd dddd dddd dddd 0 (0000) cntxctl r201 (r0x2c9) n/a camctl r202 (r0x2ca) n/a camctl r203 (r0x2cb) 0 (0000) camctl r204 (r0x2cc) 0 (0000) camctl r205 (r0x2cd) 8608 (21a0) camctl r206 (r0x2ce) 7835 (1e9b) camctl table 9: camera control registers (address page 2) (continued) register number dec (hex) register name data format (binary) default value dec (hex) module
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register list mt9m131 ds rev. h 5/15 en 20 ?semiconductor components industries, llc,2015. notes: 1. data format key: 0 = don't care bit. the exceptions: r0x200 and r0x2ff, which are hardwired r/o binary values. d = r/w bit ? = r/o bit. r207 (r0x2cf) 19018 (4a4a) camctl r208 (r0x2d0) 5773 (168d) camctl r209 (r0x2d1) 77 (004d) camctl r210 (r0x2d2) 0 (0000) camctl r211 (r0x2d3) 0 (0000) cntxctl r212 (r0x2d4) 520 (0208) camctl r213 (r0x2d5) 0 (0000) camctl r239 (r0x2ef) 8 (0008) awb r240 (r0x2f0) page map 0000 0000 0000 0ddd 0 (0000) cfg r241 (r0x2f1) byte-wise address C reserved C r242 (r0x2f2) 0 (0000) awb r243 (r0x2f3) reserved C 0 (0000) C r244 (r0x2f4) 110 (006e) colorcorr r245 (r0x2f5) 135 (0087) colorcorr r246 (r0x2f6) 54 (0036) colorcorr r247 (r0x2f7) 13 (000d) colorcorr r248 (r0x2f8) 171 (00ab) colorcorr r249 (r0x2f9) 136 (0088) colorcorr r250 (r0x2fa) 72 (0048) colorcorr r251 (r0x2fb) 87 (0057) colorcorr r252 (r0x2fc) 94 (005e) colorcorr r253 (r0x2fd) 122 (007a) colorcorr r254 (r0x2fe) 20543 (503f) colorcorr r255 (r0x2ff) 43136 (a880) colorcorr table 9: camera control registers (address page 2) (continued) register number dec (hex) register name data format (binary) default value dec (hex) module
mt9m131 ds rev. h 5/15 en 21 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description ifp register description configuration the vast majority of ifp registers associate naturally to one of the ifp modules. these modules are identified in table 9 on page 17. detailed register descriptions follow in table 10. a few registers create effects across a number of module functions. these include r0xf0 page map register (r/w); r0x106 operating mode control register (r/w); r0x108 output format control register (r/w); the r0x23e gain types and ccm threshold register?the gain threshold for ccm adjustment (r/w) colorpipe registers unless noted otherwise in this document, co lorpipe registers take effect immediately. this can result in one or more distorted output frames. these registers should be adjusted during fv low or the resulting image should be hidden for one or two frames. colorpipe resize registers are updated shortly after fv goes high. they are not exam- ined again until the next frame. table 10: colorpipe register description address page 1 register number decC hex description r5:1r0x105 - aperture correction default 0x0003 description aperture correction scale factor, used for sharpening. bit 3 enables automatic sharpnes s reduction control (see r0x233). bits 2:0 sharpening factor: 000 no sharpening. 001 25% sharpening. 010 50% sharpening. 011 75% sharpening. 100 100% sharpening. 101 125% sharpening. 110 150% sharpening. 111 200% sharpening. r6:1r0x106 - operating mode control (r/w) default 0x700e description this register specifies the operating mode of the ifp. bit 15 enables manual white balance. user can set the base matrix and color channel gains. this bit must be asserted and de-asserted with a frame in between to force ne w color correction settings to take effect. bit 14 enables auto exposure. bit 13 enables on-the-fly defect correction. bit 12 clips aperture corrections. small aperture correcti ons (< 8) are attenuated to reduce noise amplification. bit 11 load color correction matrix 1: in manual white balance mode, triggers the loading of a new base matrix in color correction and the loading of new base sensor gain ratios. 0: enables the matrix to be changed offline. bit 10 enables lens shading correction. 1: enables lens shading correction.
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description mt9m131 ds rev. h 5/15 en 22 ?semiconductor components industries, llc,2015. bit 9 reserved. bit 8 reserved. bit 7 enables flicker detection. 1: enables automatic flicker detection. bit 6 reserved for future expansion. bit 5 reserved. bit 4 bypasses color correction matrix. 1: outputs raw color, bypassing color correction. 0: normal color processing. bits 3:2 auto exposure back light compensation control. 00auto exposure sampling window is spec ified by r0x226 and r0x227 (large window). 01 auto exposure sampling window is specified by r0x22b and r0x22c (small window). 1x auto exposure sampling window is specified by th e weighted sum of the large window and the small window, with the small window weighted four times more heavily. bit 1 enables awb. 1: enables auto white balance. 0: freezes white balance at current values. bit 0 reserved for future expansion. r8:1r0x108 - output format control (r/w) default 0x0080 description this register specifies the output timing and format in conjunction with r0x13a or r0x19b (depending on the context). bits 15:10 reserved for future expansion. bit 9 flip bayer columns in processed bayer output mode. 0: column order is green, red and blue, green. 1: column order is red, green and green, blue. bit 8 flip bayer row in processed bayer output mode. 0: first row contains green and red; the second row contains blue and green. 1: first row contains blue and green; the second row contains green and red. bit 7 controls the values used for the protection bits in rec. itu-r bt.656 codes. 0: use zeros for the protection bits. 1: use the correct values. bit 5 multiplexes y (in ycbcr mode) or green (in rgb mode) channel on all channels (monochrome). 1: forces y/g onto all channels. bit 4 disables cab color output channel (cb = 128) in ycbc r mode and disables the blue color output channel (b = 0) in rgb mode. 1: forces cab to 128 or b to 0. bit 3 disables y color output channel (y = 128) in ycbcr and disables the green color output channel (g = 0) in rgb mode. 1: forces y to 128 or g to 0. bit 2 disables cr color output channel (cr = 128) in ycbcr mode and disables the red color output channel (r = 0) in rgb mode. 1: forces cr to 128 or r to 0. bit 1 toggles the assumptions about bayer vertical cfa shift. 0: row containing red comes first. 1: row containing blue comes first. table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131 ds rev. h 5/15 en 23 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description bit 0 toggles the assumptions about bayer horizontal cfa shift. 0: green comes first. 1: red or blue comes first. r37:1r0x125 - color saturation control (r/w) default 0x0005 description this register specifies th e color saturation control settings. bit 5:3 specify overall attenuation of the color saturation. 000 full color saturation. 001 75% of full saturation. 010 50% of full saturation. 011 37.5% of full saturation. 100 25% of full saturation. 101 150% of full saturation. 110 black and white bit 2:0 specify color saturation attenuation at high luminance (linearly increasing attenuation from no attenuation to monochrome at luminance of 224). 000 no attenuation. 001 attenuation starts at luminance of 216. 010 attenuation starts at luminance of 208. 011 attenuation starts at luminance of 192. 100 attenuation starts at luminance of 160. 101 attenuation starts at luminance of 96. r52:1r0x134 - luma offset (r/w) default 0x0010 description offset added to the luminance prior to output. bits 15:8 y offset in ycbcr mode. bits 7:0 offset in rgb mode. r53:1r0x135 - luma clip (r/w) default 0xf010 description clipping limits for output luminance. bits 15:8 highest value of output luminance. bits 7:0 lowest value of output luminance. r58:1r0x13a - output format control 2context a (r/w) default 0x0200 description output format control 2a. bit 14 output processed bayer data. bit 13 reserved bit 12 bit 11 enables embedding rec. itu-r bt.656 synchro nization codes in the output data. see r0x19b table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description mt9m131 ds rev. h 5/15 en 24 ?semiconductor components industries, llc,2015. bit 10 entire image processing is bypassed and raw bayer is output directly. in ycbcr or rgb mode: 0: normal operation, sensor core data flows through ifp. 1: bypass ifp and output imager data directly (full 10 bits). the image data still passes through the camera interface fifo and the 10 bits are formatted to two output bytes through the camera interface; that is, 8 + 2. data rate is effectively the same as default 16-bit /per pixe l modes. auto exposure/awb, etc. still function and control the sensor, though they are assuming some gain/correction through the colorpipe. see r0x19b bit 9 invert output pixel clock. inverts output pixe l clock. by default, this bit is asserted. 0: output data transitions on the rising edge of pi xclk for capture by the receiver on the falling edge. 1: output data transitions on the falling edge of pi xclk for capture by the receiver on the rising edge. bit 8 enables rgb output. 0: output ycbcr data. 1: output rgb format data as defined by r0x13a[7:6]. bits 7:6 rgb output format: 00 16-bit 565rgb. 01 15-bit 555rgb. 10 12-bit 444xrgb. 11 12-bit x444rgb. bits 5:4 test ramp output: 00 off. 01 by column. 10 by row. 11 by frame. bit 3 outputs rgb or ycbcr values are shifted 3 bits up. use with r0x13a[5:4] to test lcds with low color depth. bit 2 averages two nearby chrominance bytes. see r0x19b bit 1 in ycbcr mode swap c and y bytes. in rgb mode, swap odd and even bytes. see r0x19b bit 0 in ycbcr mode, swaps cb and cr channels. in rgb mode, swaps r and b channels. see r0x19b r72:10x148 - test pattern generator control (r/w) default 0x0000 description this register enables test pattern generation at the inpu t of the image processor. values greater than 0 turn on the test pattern generator. the brightness of the flat co lor areas depends on the valu e programmed (from 6C1) in this register. the value 7 produces the color bar pattern. value 0 selects the sensor image. bit 7 1: forces wb digital gains to 1.0. 0: normal operation. bits 2:0 test pattern selection. r76:10x14c - defect correctioncontext a (r/w) default 0x0000 description context a register with defect co rrection, mode enables, and calibration bits. bit 2 reserved bit 1 reserved bit 0 enables 2d defect correction. r77:10x14d - defect correctioncontext b (r/w) default 0x0000 description context b register with defect co rrection, mode enables, and calibration bits. bit 2 reserved table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131 ds rev. h 5/15 en 25 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description bit 1 reserved bit 0 enables 2d defect correction. r153:10x199 - line counter (r/o) default n/a description use line counter to determine the number of the line currently being output. bits 12:0 line count. r154:10x19a - frame counter (r/o) default n/a description use frame counter to determine th e index of the frame currently being output. bits 15:0 frame count. table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description mt9m131 ds rev. h 5/15 en 26 ?semiconductor components industries, llc,2015. r155:10x19b - output format control 2context b (r/w) default 0x0200 description output format control 2b. bit 14 output processed bayer data. bit 13 reserved. bit 12 bit 11 enables embedding rec. itu-r bt.656 synchro nization codes to the output data. see r0x13a bit 10 entire image processing is bypassed and raw bayer is output directly. in ycbcr or rgb mode: 0: normal operation, sensor core data flows through ifp. 1: bypass ifp and output imager data directly (full 10 bits). the image data still passes through the camera interface fifo and the 10 bits are formatted to 2 output bytes through the camera interf ace; that is, 8 + 2. data rate is effectively the same as default 16-bit /per pi xel modes. ae/awb, and so on, still function and control the sensor, though they are assuming some gain/ correction through the colorpipe. see r0x13a bit 9 invert output pixel clock. inverts output pixe l clock. by default, this bit is asserted. 0: output data transitions on the rising edge of pi xclk for capture by the receiver on the falling edge. 1: output data transitions on the falling edge of pi xclk for capture by the receiver on the rising edge bit 8 enables rgb output. 0: output ycbcr data. 1: output rgb format data as defined by r0x19b[7:6]. see r0x13a bits 7:6 rgb output format: 00 16-bit 565rgb. 01 15-bit 555rgb. 10 12-bit 444xrgb. 11 12-bit x444rgb. bits 5:4 test ramp output: 00 off. 01 by column. 10 by row. 11 by frame. bit 3 output rgb or ycbcr values are shifted 3 bits up. use with r0x13a[5:4] to test lcds with low color depth. bit 2 averages two nearby chrominance bytes. see r0x13a bit 1 in ycbcr mode swap c and y bytes. in rgb mode, swap odd and even bytes. see r0x13a bit 0 in ycbcr mode, swaps cb and cr channels. in rgb mode, swaps r and b channels. see r0x13a r159:10x19f - reducer horizontal pancontext b (r/w) default 0x0000 description controls reducer horizontal pan in context b bit 14 0: mt9v111-compatible origin at x = 0. 1: centered origin at 640 for more convenient zoom and resize. bits 10:0 x pan: unsigned offset from x = 0 (bit 14 = 0), or twos complement from x = 640 (bit 14 = 1). r160:10x1a0 - reducer horizo ntal zoomcontext b (r/w) default 0x0500 description controls reducer horizontal widt h of zoom window for fov in context b. bits 10:0 x zoom b. must be ? x size b r161:10x1a1 - reducer horizontal output sizecontext b (r/w) table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131 ds rev. h 5/15 en 27 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description default 0x0500 description controls reducer horizontal output size in context b. bits 10:0 x size b. must be ? x zoom b. r162:10x1a2 - reducer vertical pancontext b (r/w) default 0x0000 description controls reducer vertical pan in context b. bit 14 0: mt9v111-compatible origin at y = 0. 1: centered origin at y = 512 for more convenient zoom and resize. bits 10:0 y pan: unsigned offset from y = 0 (bit 14 = 0), or twos complement from y = 512 (bit 14 = 1). r163:10x1a3 - reducer vertical zoomcontext b (r/w) default 0x0400 description controls reducer vertical height of zoom window for fov in context b. bits 10:0 y zoom b. must be ? y size b. r164:10x1a4 - reducer vertical output sizecontext b (r/w) default 0x0400 description controls reducer vertical output size in context b. bits 10:0 y size b. must be ? y zoom b. r165:10x1a5 - reducer horizontal pancontext a (r/w) default 0x0000 description controls reducer horizontal pan in context a. bit 14 0: mt9v111-compatible offset from x = 0. 1: centered origin at 640 for more convenient zoom and resize. bits 10:0 x pan: unsigned offset from x = 0 (bit 14 = 0), or twos complement from x = 640 (bit 14 = 1). r166:10x1a6 - reducer horizo ntal zoomcontext a (r/w) default 0x0500 description controls reducer horizontal widt h of zoom window for fov in context a. bits 10:0 x zoom a. must be ? x size a. r167:10x1a7 - reducer horizontal output sizecontext a (r/w) default 0x0280 description controls reducer horizontal output size in context a. bits 10:0 x size a. must be ? x zoom a. r168:10x1a8 - reducer vertical pancontext a (r/w) default 0x0000 description controls reducer vertical pan in context a. bit 14 0: mt9v111-compatible origin at y = 0. 1: centered origin at y = 512 for more convenient zoom and resize. bits 10:0 y pan: unsigned offset from y = 0 (bit 14 = 0), or twos complement from y = 512 (bit 14 = 1). r169:10x1a9 - reducer vertical zoomcontext a (r/w) default 0x0400 description controls reducer vertical height of zoom window for fov in context a. table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description mt9m131 ds rev. h 5/15 en 28 ?semiconductor components industries, llc,2015. bits 10:0 y zoom a. must be ? y size a. r170:10x1aa - reducer vertical output sizecontext a (r/w) default 0x0200 description controls reducer vertical output size in context a. bits 10:0 y sizea. must be ? y zoom a. r171:10x1ab - reducer current horizontal zoom (r/o) default n/a description current horizontal zoom. bits 10:0 current zoom window width. after automatic zoom (r0x 1af), copy r0x1ab to the snapshot x zoom register r0x1a6 (context a) or r0x1a0 (context b) so the snapsh ot has the same fov as preview. also copy to snapshot x size register r0x1a7 (context a) or r0 x1a1 (context b) for largest snapshot. bits 15:12 reserved. mask off these bits be fore performing the above copy operation. r172:10x1ac - reducer curr ent vertical zoom (r/o) default n/a description current vertical zoom. bits 10:0 current zoom window height. after automatic zoom (r0x1af), copy r0x1ac to the snapshot y zoom register r0x1a9 (context a) or r0x1a3 (conte xt b) so the snapshot will have the same fov as preview. also copy to snapshot x size register r0x1aa (context a) or r0x1a4 (context b) for largest snapshot. bits 15:12 reserved. mask off these bits be fore performing the above copy operation. r174:10x1ae - reducer zoom step size (r/w) default 0x0504 description zoom step sizes. should be a multiple of the aspect ratio 5:4 for sxga or 4:3 vga or 11:9 for cif. bits 15:8 zoom step size in x. bits 7:0 zoom step size in y. r175:10x1af - reducer zoom control (r/w) default 0x0010 description resize interpolation and zoom control. bit 9 starts automatic zoom out in step sizes defined in r0x1ae. bit 8 starts automatic zoom in in step sizes defined in r0x1ae. bit 6 bit 5 bit 4 bit 3 auto switch to classic in terpolation at full resolution. bit 1 reserved. bit 0 reserved. r179:10x1b3 - global clock control (r/w) default 0x0002 description configures assorted aspects of the clock controller. bits 15:2 not used. bit 1 tri-states signals in standby mode. bit 0 table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131 ds rev. h 5/15 en 29 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor ifp register description r182:10x1b6 - lens vertical red knees 6 and 5 (r/w) r200:10x1c8 - global context control (r/w) default 0x0000 description defines sensor and colorpipe context for current frame. registers r0x0c8, r0x1c8, and r0x2c8 are shadows of each other. see description in r0x2c8 . it is recommended that all updates to r0xnc8 are handled by means of a write to r0x2c8. bit 15:0 see r0x2c8[15:0]. r226:10x1e2 - effects mode (r/w) default 0x7000 description this register specifies which of several special e ffects to apply to each pixel passing through the pixel pipe. bits 15:8 solarization threshold. bits 2:0 specification of the effects mode. 000 no effect (pixels pass through unchanged). 001 monochrome (chromas set to 0). 010 sepia (chromas set to the value in the effects sepia register). 011 negative (all color channels inverted). 100 solarize (luma conditionally inverted). 101 solarize2 (luma conditionally inverted, chromas inverted when luma inverted). r227:10x1e3 - effects sepia (r/w) default 0xb023 description this register specifies the chroma values for the sepia ef fect. in sepia mode, the chroma values of each pixel are set to this value. by default, this register contains a br ownish color, but it can be set to an arbitrary color. bit 15 sign of cb. bits 14:8 magnitude of cb in 0.7 fixed point. bit 7 sign of cr. bits 6:0 magnitude of cr in 0.7 fixed point. r240:10x1f0 - page map (r/w) default 0x0000 description this register specifies the register ad dress page for the two-wire interface protocol. bits 2:0 page address: 000 sensor address page. 001 colorpipe address page. 010 camera control address page. r241:10x1f1 - byte-wise address (r/w) default n/a description special address to perform 8-bit reads and writes to the sensor. for addition al information, see two-wire serial interface sample on page 63 and appendix a C serial bus description on page 61. table 10: colorpipe register descri ption address page 1 (continued) register number decC hex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers mt9m131 ds rev. h 5/15 en 30 ?semiconductor components industries, llc,2015. camera control registers register writes reach the camera control registers immediately. for non-ae/awb/ ccm registers, register writes take effect immediately. for ae/awb and ccm registers, the effects of register writes are de pendent on the state of the ae and awb engines. it may take from zero to many frames for the changes to take effect. monitor awb/ccm changes by watching for stable settings in r0x212 (current ccm position), in r0x213 (current awb red channel), and in r0x214 (current awb blue channel). monitor ae changes by watching register r0x24c (ae current luma exposure), and register r0x262 (ae digital gains monitor). table 11: camera control register description register number dechex description r38:20x226 - auto exposure wind ow horizontal boundaries (r/w) default 0x8000 description this register specifies the left an d right boundaries of the window used by the ae measurement engine. the values programmed in the registers are the fractional pe rcentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the fr ame, and 0 is the left-most edge of the frame. bits 15:8 right window boundary. bits 7:0 left window boundary. r39:20x227 - auto exposure wind ow vertical boundaries (r/w) default 0x8008 description this register specifies the top and bottom boundaries of the window used by the ae measurement engine. the values programmed in the registers are the fractional pe rcentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the top edge of the frame. bits 15:8 bottom window boundary. bits 7:0 top window boundary. r42:20x22a - wb zone validity limits (r/w) r43:20x22b - auto exposure center window horizontal boundaries (r/w) default 0x6020 description this register specifies the left an d right boundaries of the window used by the ae measurement engine in backlight compensation mode. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. bits 15:8 right window boundary. bits 7:0 left window boundary.
mt9m131 ds rev. h 5/15 en 31 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers r44:20x22c - auto exposure center window vertical boundaries (r/w) default 0x6020 description this register specifies the top and bottom boundaries of the window used by the ae measurement engine in backlight compensation mode. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, an d 0 is the top edge of the frame. bits 15:8 bottom window boundary. bits 7:0 top window boundary. r45:20x22d - awb window boundaries (r/w) default 0xf0a0 description this register specifies the boundaries of the window used by the awb measurement engine. essentially, it describes the awb measurement window in terms relative to the size of the imagehorizontally, in units of 1/10ths of the width of the image; vertically, in units of 1/16 of the height of the image. so although the positioning is highly quantized, the window re mains roughly in place as the resolution changes. bits 15:12 bottom window bound ary (in units of 1 block). bits 11:8 top window boundary (in units of 1 block). bits 7:4 right window boundary (in units of 2 blocks). bits 3:0 left window boundar y (in units of 2 blocks). r46:20x22e - auto exposure target and precision control (r/w) default 0x0c4a description this register specifies the luma target of the ae algorith m and the size of the window/range around the target in which no ae adjustment is made. this window is centered on target, but the value programmed in the register is 1/2 of the window size. bits 15:8 half-size of the ae stability window/range. bits 7:0 luma value of the ae target. r47:20x22f - auto exposure speed and sensitivity controlcontext a (r/w) default 0xdf20 description this register specifies the speed an d sensitivity to changes of ae in context a. bit 15 reserved. bit 14 bits 13:12 bit 11 reserved. bit 10 reserved. bit 9 reserved. bits 8:6 factor of reduction of the difference between current luma and target luma. in one adjustment ae advances from current luma to target as follows: 000 1/4 way going down, 1/8 going up. 001 1/4 way in both directions. 010 1/2 way in both directions. 011 1/2 way going down, 1/4 going up. 100 all the way in both directions (fast adaptation!). 101 3/4 way in both directions. 110 7/8 way in both directions. 111 reserved. currently the same as 100 bit 5 reserved. table 11: camera control register description (continued) register number dechex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers mt9m131 ds rev. h 5/15 en 32 ?semiconductor components industries, llc,2015. bits 4:3 auto exposure luma is updated every n frames, where n is given by this field. bits 2:0 hysteresis control through time-averaged smoothing of luma data. luma measurements for ae are time-averaged as follows: 000 auto exposure luma = current luma. 001 auto exposure luma = 1/2 current luma + 1/2 buffered value. 010 auto exposure luma = 1/4 current luma + 3/4 buffered value. 011 auto exposure luma = 1/8 current luma + 7/8 buffered value. 100 auto exposure luma = 1/16 current luma + 15/16 buffered value. 101 auto exposure luma = 1/32 current luma + 31/32 buffered value. 110 auto exposure luma = 1/64 current luma + 63/64 buffered value. 111 auto exposure luma = 1/128 current luma + 127/128 buffered value. r55:20x237 - auto exposure gain zone limits (r/w) r57:20x239 - auto exposure line sizecontext a (r/w) r91:20x25b - flicker control (r/w) default 0x0002 description primary flicker control register. bit 15 (read only) 50hz/60hz detected. 0: 50hz detected. 1: 60hz detected. bit 2 bit 1 when in manual flicker mode (r0x25b[0] = 1), defines which flicker frequency to avoid. 0: forces 50hz detection. 1: forces 60hz detection. bit 0 0: auto flicker detection. 1: manual mode. r98:20x262 - auto exposure digital gains monitor (r/w*) default n/a description these digital gains are applied within the ifp; they are independent of the imager gains. table 11: camera control register description (continued) register number dechex description
mt9m131 ds rev. h 5/15 en 33 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers bits 15:8 post-lens-correction digital gain (*writable if ae is disabled). bits 7:0 pre-lens-correction digital gain (*writable if ae is disabled). r103:20x267 - auto exposure digital gain limits (r/w) default 0x4010 description this register specifies the up per limits of the digital gains used by the ae algorithm. the values programmed to this register are 16 times the absolute gain values. the value of 16 represents the gain 1.0. bits 15:8 maximum limit on post-lens-correction digital gain. bits 7:0 maximum limit on pr e-lens-correction digital gain. r135:20x287 - auto exposure gain zone 6 deltas (r/w) r156:20x29c - auto exposure speed and sensitivity controlcontext b (r/w) default 0xdf20 description this register specifies the speed and sensitivity to ae changes in context b. bit 15 reserved. bit 14 bits 13:12 bit 11 reserved. bit 10 reserved. bit 9 reserved. bits 8:6 factor of reduction of the difference between current luma and target luma. in one adjustment, ae advances from current luma to target as follows: 000 1/4 way going down, 1/8 going up. 001 1/4 way in both directions. 010 1/2 way in both directions. 011 1/2 way going down, 1/4 going up. 100 all the way in both directions (fast adaptation!). 101 3/4 way in both directions. 110 7/8 way in both directions. 111 reserved. currently the same as 100. bit 5 reserved. bits 4:3 auto exposure luma is updated every n frames, where n is given by this field. table 11: camera control register description (continued) register number dechex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers mt9m131 ds rev. h 5/15 en 34 ?semiconductor components industries, llc,2015. bits 2:0 hysteresis control through time-averaged smoothing of luma data. luma measurements for ae are time-averaged as follows: 000 auto exposure luma = current luma. 001 auto exposure luma = 1/2 current luma + 1/2 buffered value. 010 auto exposure luma = 1/4 current luma + 3/4 buffered value. 011 auto exposure luma = 1/8 current luma + 7/8 buffered value. 100 auto exposure luma = 1/16 current luma + 15/16 buffered value. 101 auto exposure luma = 1/32 current luma + 31/32 buffered value. 110 auto exposure luma = 1/64 current luma + 63/64 buffered value. 111 auto exposure luma = 1/128 current luma + 127/128 buffered value. r180:2reserved r200:20x2c8 - global context control (r/w) default 0x0000 description defines sensor and colorpipe context for current frame. context a is typically used to define preview or viewfinder mode, while context b is typically used for snapshots. the bits of this register directly control the respective functions, so care must be taken when writing to this re gister if a bad frame is to be avoided during the context switch. bit 15 controls assertion of sensor restart on update of global context control register. this helps ensure that the very next frame is generated with the new context (a problem with regard to exposure due to the rolling shutter). this bit is automatically cleared once the restart has occurred. 0: do not restart sensor. 1: restart sensor. bit 14 reserved. bit 13 reserved. bit 12 defect correction context. see r0x14c and r0x14d. 0: context a 1: context b bit 11 bit 10 resize/zoom context. switch resize/zoom contexts: 0: context a 1: context b bit 9 output format control 2 context. see r0x13a and r0x19b. 0: context a 1: context b bit 8 gamma table context. 0: context a 1: context b bit 7 arm xenon flash. bit 6 blanking control. this is primarily for use by the inte rnal sequencer when taking automated (for example, flash) snapshots. setting this bit stops frames from being sent ov er the bt656 external pixel interface. this is useful for ensuring that the desired frame during a snapshot sequence is the only frame captured by the host. 0: do not blank frames to host. 1: blank frames to host bit 5 reserved. bit 4 reserved. bit 3 sensor read mode context (skip mode, power mode, see r0x33:0 and r0x32:0. 0: context a 1: context b table 11: camera control register description (continued) register number dechex description
mt9m131 ds rev. h 5/15 en 35 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor camera control registers note: registers marked (r/w*) are normally read-o nly (r/o) registers, except under special circum- stances (detailed in the register description), when some or all bits of the register become read- writable (r/w). bit 2 led flash on: 0: turn off led flash 1: turn on led flash bit 1 vertical blanking context: 0: context a 1: context b bit 0 horizontal blanking context: 0: context a 1: context b r240:20x2f0 - page map (r/w) default 0x0000 description this register specifies the register a ddress page for the two-wire interface protocol. bits 2:0 page address: 000 sensor address page. 001 colorpipe address page. 010 camera control address page. r241:20x2f1 - byte-wise address (r/w) default n/a description special address to perform 8-bit reads and writes to the sensor. for additional information, see two-wire serial interface sample on page 63 and appendix a C serial bus description on page 61. table 11: camera control register description (continued) register number dechex description
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core overview mt9m131 ds rev. h 5/15 en 36 ?semiconductor components industries, llc,2015. sensor core overview the sensor consists of a pixel array of 1316 x 1048 total, an analog readout chain, 10-bit adc with programmable gain and black offset, and timing and control. figure 6: sensor core block diagram pixel data format pixel array structure the mt9m131 sensor core pixel array is configured as 1316 columns by 1048 rows (shown in figure 7). the first 26 columns and the first 8 rows of pixels are optically black, and can be used to monitor the black level. th e last column and the last 7 rows of pixels also are optically black. the black row data is used internally for the automatic black level adjustment. however, the first 8 black rows can also be read out by setting the sensor to raw data output mode (r0x022). there are 1289 columns by 1033 rows of opti- cally-active pixels th at provide a 4-pixel boundary ar ound the sxga (1280 x 1024) image to avoid boundary effects during color in terpolation and correction. the additional active column and additional active row are used to enable horizo ntally and vertically mirrored readout to start on the same color pixel. figure 7: pixel array description communication bus to ifp 10-bit data to ifp sync signals clock control register analog processing active-pixel sensor (aps) array timing and control adc (1315, 1047) 26 black colum ns 7 black rows 8 black rows (0, 0) 1 black column sxga (1280 x 1024) + 4-pixel boundary for color correction + additional active column + additional active row = 1289 x 1033 active pixels
mt9m131 ds rev. h 5/15 en 37 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor pixel data format the mt9m131 sensor core uses an rgb bayer color pattern, as shown in figure 8. the even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. even -numbered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. because there are odd numbers of rows and columns, the color order can be preserved during mirrored readout. figure 8: pixel color pattern detail (top right corner) output data format the mt9m131 sensor core image data is read out in a progressive scan. valid image data is surrounded by horizontal blanking and ve rtical blanking, shown in figure 9. lv is high during the shaded region of the figure. fv timing is described in ?appendix a ? serial bus description? on page 61. figure 9: spatial illustration of image readout black pixels column readout direction . . . ... row readout d irection g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b pixe l (26, 8) p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core register list mt9m131 ds rev. h 5/15 en 38 ?semiconductor components industries, llc,2015. sensor core register list table 12: sensor registers (address page 0) 0 = don't care bit; d = r/w bit; ? = r/o bit. the exce ptions: rx00:0 and r0xff:0, which are hardwired r/o binary values. register number dec (hex) register name data format (binary) default value dec (hex) 0 (0x00) chip version 0001 0100 0011 1010 (lsb) 5178 (0x143a) 1 (0x01) row start 0000 0ddd dddd dddd 12 (0x000c) 2 (0x02) column start 0000 0ddd dddd dddd 30 (0x001e) 3 (0x03) window height 0000 0ddd dddd dddd 1024 (0x0400) 4 (0x04) window width 0000 0ddd dddd dddd 1280 (0x0500) 5 (0x05) horizontal blankingcontext b 00dd dddd dddd dddd 388 (0x0184) 6 (0x06) vertical blankingcontext b 0ddd dddd dddd dddd 42 (0x002a) 7 (0x07) horizontal blankingcontext a 00dd dddd dddd dddd 190 (0x00be) 8 (0x08) vertical blankingcontext a 0ddd dddd dddd dddd 17 (0x0011) 9 (0x09) shutter width dddd dddd dddd dddd 537 (0x0219) 10 (0x0a) row speed ddd0 000d dddd dddd 17 (0x0011) 11 (0x0b) extra delay 00dd dddd dddd dddd 0 (0x0000) 12 (0x0c) shutter delay 00dd dddd dddd dddd 0 (0x0000) 13 (0x0d) reset d000 00dd 00dd dddd 8 (0x0008) 32 (0x20) read modecontext b dd00 0ddd dddd dddd 768 (0x0300) 33 (0x21) read modecontext a 0000 0d00 0000 dd00 1036 (0x040c) 34 (0x22) 297 (0x0129) 35 (0x23) flash control ??dd dddd dddd dddd 1544 (0x0608) 36 (0x24) 32875 (0x806b) 43 (0x2b) green1 gain 0000 0ddd dddd dddd 32 (0x0020) 44 (0x2c) blue gain 0000 0ddd dddd dddd 32 (0x0020) 45 (0x2d) red gain 0000 0ddd dddd dddd 32 (0x0020) 46 (0x2e) green2 gain 0000 0ddd dddd dddd 32 (0x0020) 47 (0x2f) global gain 0000 0ddd dddd dddd 32 (0x0020) 48 (0x30) 1066 (0x042a) 49 (0x31) reserved C 7168 (0x1c00) 50 (0x32) reserved C 0 (0x0000) 51 (0x33) reserved C 841 (0x0349) 52 (0x34) reserved C 49177 (0xc019) 54 (0x36) reserved C 61680 (0xf0f0) 55 (0x37) reserved C 0 (0x0000) 59 (0x3b) reserved C 33 (0x0021) 60 (0x3c) reserved C 6688 (0x1a20) 61 (0x3d) reserved C 8222 (0x201e) 62 (0x3e) reserved C 8224 (0x2020) 63 (0x3f) reserved C 8224 (0x2020) 64 (0x40) reserved C 8220 (0x201c) 65 (0x41) 215 (0x00d7) 66 (0x42) reserved C 1911 (0x0777) 89 (0x59) 12 (0x000c) 90 (0x5a) reserved C 49167 (0xc00f)
mt9m131 ds rev. h 5/15 en 39 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core register list 91 (0x5b) n/a 92 (0x5c) n/a 93 (0x5d) n/a 94 (0x5e) n/a 95 (0x5f) 8989 (0x231d) 96 (0x60) 128 (0x0080) 97 (0x61) 0 (0x0000) 98 (0x62) 0 (0x0000) 99 (0x63) 0 (0x0000) 100 (0x64) 0 (0x0000) 101 (0x65) reserved C 0 (0x0000) 112 (0x70) reserved C 31498 (0x7b0a) 113 (0x71) reserved C 31498 (0x7b0a) 114 (0x72) reserved C 6414 (0x190e) 115 (0x73) reserved C 6159 (0x180f) 116 (0x74) reserved C 22322 (0x5732) 117 (0x75) reserved C 22068 (0x5634) 118 (0x76) reserved C 29493 (0x7335) 119 (0x77) reserved C 12306 (0x3012) 120 (0x78) reserved C 30978 (0x7902) 121 (0x79) reserved C 29958 (0x7506) 122 (0x7a) reserved C 30474 (0x770a) 123 (0x7b) reserved C 30729 (0x7809) 124 (0x7c) reserved C 32006 (0x7d06) 125 (0x7d) reserved C 12560 (0x3110) 126 (0x7e) reserved C 126 (0x007e) 128 (0x80) reserved C 127 (0x007f) 129 (0x81) reserved C 127 (0x007f) 130 (0x82) reserved C 22282 (0x570a) 131 (0x83) reserved C 22539 (0x580b) 132 (0x84) reserved C 18188 (0x470c) 133 (0x85) reserved C 18446 (0x480e) 134 (0x86) reserved C 23298 (0x5b02) 135 (0x87) reserved C 92 (0x005c) 200 (0xc8) context control d000 0000 d000 dddd 0 (0x0000) 240 (0xf0) page map 0000 0000 0000 0ddd 0 (0x0000) 241 (0xf1) byte-wise address reserved reserved 245 (0xf5) reserved C 2047 (0x07ff) 246 (0xf6) reserved C 2047 (0x07ff) 247 (0xf7) reserved C 0 (0x0000) 248 (0xf8) reserved C 0 (0x0000) 249 (0xf9) reserved C 124 (0x007c) 250 (0xfa) reserved C 0 (0x0000) 251 (0xfb) reserved C 0 (0x0000) table 12: sensor registers (a ddress page 0) (continued) 0 = don't care bit; d = r/w bit; ? = r/o bit. the exce ptions: rx00:0 and r0xff:0, which are hardwired r/o binary values. register number dec (hex) register name data format (binary) default value dec (hex)
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core register list mt9m131 ds rev. h 5/15 en 40 ?semiconductor components industries, llc,2015. 252 (0xfc) reserved C 0 (0x0000) 253 (0xfd) reserved C 0 (0x0000) 255 (0xff) chip version 0001 0100 0011 1010 5178 (0x143a) table 12: sensor registers (a ddress page 0) (continued) 0 = don't care bit; d = r/w bit; ? = r/o bit. the exce ptions: rx00:0 and r0xff:0, which are hardwired r/o binary values. register number dec (hex) register name data format (binary) default value dec (hex)
mt9m131 ds rev. h 5/15 en 41 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers sensor core registers sensor registers are generally updated before the next fv is asserted. see the column titled ?synced to frame start? in table 13 for per-register information. note: notation used in the sensor core register description table: sync?d to frame start 0 = not applicable, for exam ple, read-only register. n = no. the register value is updated and used immediately. y = yes. the register value is updated at ne xt frame start as long as the synchronize changes bit is ?0.? frame star t is defined as when the first dark row is read out. by default, this is 8 rows before fv goes high. bad frame a bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. 0 = not applicable, for exam ple, read-only register. n = no. changing the register value does not produce a bad frame. y = yes. changing the register value might produce a bad frame. ym = yes, but the bad frame is masked out unless the ?show bad frames? feature is enabled. read/write r?read-only register/bit. w?read/write register/bit. table 13: sensor core register descriptions bit field description default (hex) synced to frame start bad frame read/ write r0:00x000 - chip version (r/o) bits 15:0 hardwired read-only. 0x143a r r1:00x001 - row start bits 10:0 row start the first row to be read out (not counting dark rows that may be read). to window the image down, se t this register to the starting y value. setting a value less than 8 is not recommended since the dark rows should be read using r0x022. 0xc y ym w r2:00x002 - column start bits 10:0 col start the first column to be read out (not counting dark columns that may be read). to window the image down, set this register to the starting x value. setting a value below 0x18 is not recommended since readout of dark columns should be controlled by r0x022. 0x1e y ym w r3:00x003 - window height bits 10:0 window height number of rows in the image to be read out (not counting dark rows or border rows that may be read). 0x400 y ym w r4:00x004 - window width bits 10:0 window width number of columns in image to be read out (not counting dark columns or border columns that may be read). 0x500 y ym w r5:00x005 - horizontal blankingcontext b
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers mt9m131 ds rev. h 5/15 en 42 ?semiconductor components industries, llc,2015. bits 10:0 horizontal blanking b number of blank columns in a row when context b is chosen (r0x0c8[0] = 1). if set smalle r than the minimum value, the minimum value is used. with default settings, the minimum horizontal blanking is 202 colu mns in full-powe r readout mode and 114 columns in low-power readout mode. 0x184 y ym w r6:00x006 - vertical blankingcontext b bits 14:0 vertical blanking b number of blank rows in a frame when context b is chosen (r0x0c8[1] = 1). this number must be equal to or larger than the number of dark rows read out in a frame specified by r0x022. 0x2a y n w r7:00x007 - horizontal blankingcontext a bits 10:0 horizontal blanking a number of blank columns in a row when context a is chosen (r0x0c8[0] = 0). the extra columns are added at the beginning of a row. if set smaller than the minimum value, the minimum value is used. with default settings, the minimum horizontal blanking is 202 columns in full-power readou t mode and 114 columns in low- power readout mode. 0xbe y ym w r8:00x008 - vertical blankingcontext a bits 14:0 vertical blanking a number of blank rows in a frame when context a is chosen (r0x0c8[1] = 1). this number must be equal to or larger than the number of dark rows read out in a frame specified by r0x022. 0x11 y n w r9:00x009 - shutter width bits 15:0 shutter width integration time in number of rows. in addition to this register, the shutter delay register (r0x00c) and the overhead time influences the integration time for a given row time. 0x219 y n w r10:00x00a - row speed bits 15:13 reserved. C C C C bit 8 invert pixel clock invert pixel clock. when set, lv, fv, and data_out are set to the falling edge of pixclk. when clear, they are set to the rising edge if there is no pixel clock delay. 0x0 n 0 w bits 7:4 delay pixel clock delay pixclk in half-master-clock cycles. when set, the pixel clock can be delayed in increments of half-master- clock cycles compared to the synchronization of fv, lv, and data_out. 0x1 n 0 w bits 3:0 pixel clock speed pixel clock period in master cloc ks when full-power readout mode is used (r0x020/0x021, bit 10 = 0). in this case, the adc clock has twice the clock period. if low-power readout mode is used, the pixel clock period is automatically doubled, so the adc clock period remains the same for one programmed register value. the value 0 is not allowed, and 1 is used instead. 0x1 y ym w r11:00x00b - extra delay bits 13:0 extra delay extra blanking inserted between frames specified in pixel clocks. can be used to get a more exact frame rate. for integration times less than a frame, however, it might affect the integration times for parts of the image. 0x0 y 0 w table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131 ds rev. h 5/15 en 43 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers r12:00x00c - shutter delay bits 10:0 shutter delay the amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. this variable is automatically halved in low-power readout mode, so the time in use remains the same. this register has an upper value defined by the fact that the reset needs to finish prior to readout of that row to prevent changes in the row time. 0x0 y n w r13:00x00d - reset bit 15 synchronize changes 0: normal operation, updates changes to registers that affect image brightness at the next frame boundary (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row mirror. 1: do not update any changes to these settings until this bit is returned to 0. all registers that are frame synchronized are affected by this bit setting. 0x0 n 0 w bit 9 restart bad frames when set, a forced restart occurs when a bad frame is detected. this can shorten the delay when waiting for a good frame because the delay when masking out a bad frame is the integration time rather than the full frame time. 0x0 n 0 w bit 8 show bad frames 0: only output good frames (default) a bad frame is defined as the first frame following a change to: window size or position, horizo ntal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 1: output all frames (including bad frames) 0x0 n 0 w bit 5 reset soc this reset signal is fed directly to the soc part of the chip, and has no functionality in a stand-alone sensor. 0x0 n 0 w bit 4 output disable when set, the output signals are tri-stated. 0x0 n 0 w bit 3 chip enable 0: stop sensor readout. 1: normal operation. when this is returned to 1, sensor readout restarts and begins resetting the starting row in a new frame. to reduce the digital power, the master clock to the sensor can be disabled or standby can be used. 0x1 n ym w bit 2 analog standby 0: normal operation (default) 1: disable analog circuitry. whenever this bit is set to 1 the chip enable bit (bit 3) should be set to 0. 0x0 n ym w bit 1 restart setting this bit causes the sen sor to abandon the current frame and start resetting the first row. the delay before the first valid frame is read out equals the integration time. this bit always reads 0. 0x0 n ym w bit 0 reset setting this bit puts the sensor in reset mode; this sets the sensor to its default power-up state. clearing this bit resumes normal operation. 0x0 n ym w r32:00x020 - read modecontext b bit 15 xor line valid 0: lv determined by bit 9. ineffective if continuous lv is set. 1: lv = continuous lv xor fv. 0x0 n 0 w table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers mt9m131 ds rev. h 5/15 en 44 ?semiconductor components industries, llc,2015. bit 14 continuous line valid 0: normal lv (default, no line valid during vertical blanking). 1: continuous lv (continue producing lv during vertical blanking). 0x0 n 0 w bit 10 power readout mode context b when read mode context b is selected (r0x0c8[3] = 1): 0: full-power readout mo de, maximum readout speed. 1: low-power readout mode. maxi mum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for th e pixel clock speed register. 0x0 y ym w bit 9 show border this bit indicates whether to show the border enabled by bit 8. when bit 8 is 0, this bit has no meaning. when bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). 0x1 n 0 w bit 8 oversized when this bit is set, a 4-pixel bo rder is output around the active image array independent of readou t mode (skip, zoom, mirror, and so on). setting this bit therefore adds 8 to the numbers of rows and columns in the frame. 0x1 y ym w bit 7 0x0 y ym w bit 5 column skip 4x 0: normal readout. 1: read out 2 columns, and then skip 6 columns (as with rows). 0x0 y ym w bit 4 row skip 4x 0: normal readout. 1:readout 2 rows, and then skip 6 rows (that is, row 8, row 9, row 16, row 17). 0x0 y ym w bit 3 column skip 2x context b when read mode context b is selected (r0x0c8[3] = 1): 0: normal readout. 1: read out 2 columns, and then skip 2 columns (as with rows). 0x0 y ym w bit 2 row skip 2x context b when read mode context b is selected (r0x0c8[3] = 1): 0: normal readout. 1: read out 2 rows, then skip 2 rows (that is, row 8, row 9, row 12, row 13). 0x0 y ym w bit 1 mirror columns read out columns from right to left (mirrored). when set, column readout starts from column (col start + col size) and continues down to (col start + 1). when clear, readout starts at col start and continues to (col start + col size 1). this ensures that the starting color is maintained. 0x0 y ym w bit 0 mirror rows read out rows from bottom to top (upside down). when set, row readout starts from row (row start + row size) and continues down to (row start + 1). when clear, readout starts at row start and continues to (row start + row size 1). this ensures that the starting color is maintained. 0x0 y ym w r33:00x021 - read modecontext a bit 10 power readout mode context a when read mode context a is selected (r0x0c8[3] = 0): 0: full-power readout mo de, maximum readout speed. 1: low-power readout mode. maxi mum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for th e pixel clock speed register. 0x1 y ym w bit 3 column skip 2x context a when read mode context a is selected (r0x0c8[3] = 0): 0: normal readout. 1: readout 2 columns, and then skip 2 columns (as with rows). 0x1 y ym w table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131 ds rev. h 5/15 en 45 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers bit 2 row skip 2x context a when read mode context a is selected (r0x0c8[3] = 0): 0: normal readout. 1: readout 2 rows, and then skip 2 rows (that is, row 8, row 9, row 12, row 13). 0x1 y ym w r35:00x023 - flash control bit 15 flash strobe read-only bit that indicates whether flash_strobe is enabled. 0x0 0 0 r bit 14 reserved. bit 13 xenon flash enable xenon flash. when set, flash_strobe output is pulsed high for the programmed period during vertical blanking. this is achieved by keeping the integration time equal to one frame and the pulse width less than the vertical blanking time. 0x0 y n w bits 12:11 frame delay delay of the flash pulse measured in frames. 0x0 n n w bit 10 end of reset 0: in xenon mode, the flash should be enabled after the readout of a frame. 1: in xenon mode, the flash should be triggered after the resetting of a frame. 0x1 n n w bit 9 every frame 0: flash should be enabled for 1 frame only. 1: flash should be enabled every frame. 0x1 n n w bit 8 led flash enables led flash. when set, flash_strobe goes on prior to the start of a frame reset. when disabled, the flash_strobe remains high until readout of the current frame completes. 0x0 y y w bits 7:0 xenon count length of flash_strobe pulse wh en xenon flash is enabled. the value specifies the length in 1,02 4 master clock cycle increments. 0x08 n n w r43:00x02b - green1 gain bits 6:0 initial gain initial gain = bits (6:0) x 0.03125. 0x20 y n w bits 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 y n w bits 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0x0 y n w r44:00x02c - blue gain bits 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0x0 y n w bits 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 y n w bits 6:0 initial gain initial gain = bits (6:0) x 0.03125. 0x20 y n w r45:00x02d - red gain table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers mt9m131 ds rev. h 5/15 en 46 ?semiconductor components industries, llc,2015. bits 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain). 0x0 y n w bits 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 y n w bits 6:0 initial gain initial gain = bits (6:0) x 0.03125. 0x20 y n w r46:00x02e - green2 gain bits 10:9 digital gain total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain threshold (each bit gives 2x gain). 0x0 y n w bits 8:7 analog gain analog gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 y n w bits 6:0 initial gain initial gain = bits (6:0) x 0.03125. 0x20 y n w r47:00x02f - global gain bits 10:0 global gain this register can be used to set all 4 gains at once. when read, it returns the value stored in r0x2b. 0x20 y n w r91:00x05b - dark green1 frame average (r/o) r92:00x05c - dark blue frame average (r/o) r200:00x0c8 - context control bit 15 restart setting this bit causes the sen sor to abandon the current frame and start resetting the first row. same physical register as r0x00d[1]. 0x0 n ym w bit 7 xenon flash enable enable xenon flash. same phys ical register as r0x023[13]. 0x0 y n w bit 3 read mode select 0: use read mode, context a, r0x021. 1: use read mode, context b, r0x020. note that bits found only in the read mode context b register is always taken from that register. 0x0 y ym w bit 2 led flash enable enable led flash. same physical register as r0x023[8]. 0x0 y y w bit 1 vertical blanking select 0: use vertical blanking, context a, r0x008. 1: use vertical blanki ng, context b, r0x006. 0x0 y ym w bit 0 horizontal blanking select 0: use horizontal blanking, context a, r0x007. 1: use horizontal blanking, context b, r0x005. 0x0 y ym w table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131 ds rev. h 5/15 en 47 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor core registers r240:00x0f0 - page map bits 2:0 page map page mapping register. must be kept at 0 to be able to write to/ read from sensor. used in the soc to access other pages with registers. 0x0 n 0 w r241:00x0f1 - byte-wise address bit 0 byte-wise address special address to perform 8-bit (instead of 16-bit) reads and writes to the sensor. for additi onal information, see two-wire serial interface sample on page 63 and appendix a C serial bus description on page 61. n/a 0 0 0 r255:00x0ff - chip version (r/o) bits 15:0 hardwired value. 0x143a r table 13: sensor core regist er descriptions (continued) bit field description default (hex) synced to frame start bad frame read/ write
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing mt9m131 ds rev. h 5/15 en 48 ?semiconductor components industries, llc,2015. sensor read modes and timing this section provides an overview of typical usage modes for the mt9m131. it focuses on two primary configurations: the first is suitable for low-power viewfinding, the second for full resolution snapshots. it also desc ribes mechanisms for switching between these modes. contexts the mt9m131 supports hardware-accelerated context switching. a number of parame- ters have two copies of their setup registers; this allows two contexts to be loaded at any given time. these are referred to as contex t a and context b. context selection for any single parameter is determined by the global context control register (gccr, see r0x2c8). there are copies of this register in each address page. a write to any one of them has the identical effect. however, a read from address page 0 only returns the subset bits of r0xc8 that are specific to the sensor core. the user can employ contexts for a variety of purposes; thus the generic naming conven- tion. one typical usage model is to define context a as viewfinder or preview mode and context b as snapshot mode. the device defaul ts are configured with this in mind. this mechanism enables the user to have settings for viewfinder and snapshot modes loaded at the same time, and then switch between them with a single write to r0x2c8. viewfinder/preview and full-resolution/snapshot modes in the mt9m131, the sensor core supports two primary readout modes: low-power preview mode and full-resolution snapshot mode. low-power preview mode qsxga (640 x 512) images are generated at up to 30 fps. the reduced-size images are generated by skipping pixels in the sensor, that is, decima tion. the key sensor registers that define this mode are read mode contex t a register (r0x021) and read mode context b register (r0x020). only certain bits in these registers are context switchable; any bits that do not have multiple contexts are always defined by their values in r0x020. any active sets of these registers are define d by the state of r0xnc8[3]. on reset, r0xnc8[3] = 0 selecting r0x021; setups specific to preview are defined by this register. full-resolution snapshot mode sxga (1280 x 1024) images are generated at up to 15 fps. this is typically selected by setting r0x0c8[3] = 1 selecting r0x020 (context b) as the primary read mode register. switching modes typically, switching to full-resolution or snapshot mode is achieved by writing r0x2c8 = 0x9f0b. this restarts the sensor and sets most contexts to context b. following this write, a read from r0x1c8 or r0x2c8 results in 0x1f0b being read. note that the most significant bit (msb) is cleared automa tically by the sensor. a read from r0x0c8 results in 0x000b, as only the lower 4 bits and the restart msb are implemented in the sensor core.
mt9m131 ds rev. h 5/15 en 49 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing clocks the sensor core is a master in the system. the sensor core frame rate defines the overall image flow pipeline frame rate. horizontal an d vertical blanking are influenced by the sensor configuration, and are also a functi on of certain ifp functions?particularly resize. the relationship of the primar y clocks are depicted in figure 10. figure 10: primary sensor core clock relationships the ifp typically generates up to 16 bits per pixel, for example ycbcr or 565rgb, but has only an 8-bit port through which to communicate this pixel data. there is no phase locked loop (pll), so the primary input cl ock (extclk) must be twice the fundamental pixel rate (defined by the sensor pixel clock). to generate sxga images at 15 fps, the sensor core requires a clock in the 24 to 27 mhz range; this is also the fundamental pixel cl ock rate (sensor pixel clock) for full-power operation. to achieve this pixel rate, extclk must be in the 48 to 54 mhz range. the device defaults assume a 54 mhz cl ock. minimum clock frequency is 2 mhz. 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel 0.5 pixel/clock sensor core colorpipe output fifo div by 2 div by n sensor pixel clock sensor master clock e xtclk
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing mt9m131 ds rev. h 5/15 en 50 ?semiconductor components industries, llc,2015. primary operating modes the mt9m131 supports two primary modes of operation with respect to the sensor core that affect pixel rate, frame rate, and blanking. full-power readout mode the sensor is in full resolution mode, generating 1.3 megapixels (sxga = 1,280 x 1,024 + border) for interpolation. the sxga image fe d from the sensor to the colorpipe can be resized in the colorpipe, but the frame rate is still defined by sensor core operation. in full-power readout mode, with full fov, the frame rate is invariant with the final image size: low-power readout mode running under low-power readout, the sensor is in skip mode, and generates qsxga frames (640 x 512 + border = 336,960 pixels). this full fov qsxga image can be resized, but only to resolutions smaller than qsxga. the frame rate is defined by the operating mode of the sensor: context: typically context b sensor read mode settings: no skipping full-power readout, that is, full data rate sensor pixel clock: 27 mhz for 54 mhz master clock: maximum pixel rate of 27 megapixels per second maximum frame rate: for 54 mhz master clock, 15 fps context: typically context a sensor read mode settings: row skip 2x column skip 2x low-power readout maximum data rate is half that of full-power readout sensor pixel clock: 13.5 mhz for 54 mhz master clock: maximum pixel rate of 13.5 megapixels per second maximum frame rate: for 54 mhz master clock, 30 fps
mt9m131 ds rev. h 5/15 en 51 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing tuning frame rates actual frame rates can be tuned by adjusting various sensor parameters. the sensor registers are in page 0, thus the ?0? at the begining of each register address: in the mt9m131, the sensor core adds 4 bord er pixels all the way around the image, taking the active im age size to 1288 x 1032 in full-power snapshot resolution, and 648 x 520 when skipping rows in low-power preview resolution. this is achieved through the default settings: ? read mode context b: r0x020 ? oversize and show border bits are set by default ? oversize and show border bits are not context switchable, thus their location only in read mode context b default blanking calculations the mt9m131 default blanking calculations are a function of context, as follows: [reg | reg]: ?reg low-power readout = context a, typically used for viewfinder ?reg full power readout = context b, typically used for snapshots table 14: register address functions register function r0x004 window width, typi cally 1280 in the mt9m131 r0x003 window height, typically 1024 in the mt9m131 low-power readout modecontext a r0x007 horizontal blanking, default is 190 (units of sensor pixel clocks) r0x008 vertical blanking, default is 17 (rows including black rows) full-power readout modecontext b r0x005 horizontal blanking, default is 388 (units of sensor pixel clocks) r0x006 vertical blanking, default is 42 (rows including black rows) table 15: blanking parameter calculations parameter calculation pc_period full-power readout: (2/54)s = 0.0370s sensor pixel clock period low-power readout: (4/54)s = 0.0185s a: active data time (per line): full-power readout: a = 1,288 x (2/54)s = 47.704s r0x004 + 8 (border) x pc_period low-power readout: a = 648 x (4 / 54)s = 48.000 s q: horizontal blanking: full-power readout: q = 388 x (2/54)s = 14.370s [r0x005 | r0x007] x pc_period low-power readout: q = 190 x (4/54)s = 14.074s row time = q + a: full-power readout: 62.074s low-power readout: 62.074s p: frame start / end blanking: full-powe r readout: p = 4 x (2/54)s = 0.148s 4 x pc_period low-power readout: p = 4 x (4 / 54)s = 0.296s v: vertical blanking: full-power readout: v = (42 x 62.074) + (14.370 - 0.296) = 2,621.333s [r0x006 | r0x008] x (q + a) + (q - 2 x p) low-power readout: v = (17 x 62.074) + (14.074 - 0.593) = 1,068.740s
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing mt9m131 ds rev. h 5/15 en 52 ?semiconductor components industries, llc,2015. notes: 1. the line rate (row rate) is the same for both low power and full power re adout modes. this ensures that when switching modes, exposure time do es not change; the pre-existing shutter width remains valid. user blanking calculations when calculating blanking for different cl ock rates, minimum values for horizontal blanking and vertical blanki ng must be taken into account. table 16 shows minimum values for each register. exposure and sensor context switching the mt9m131 incorporates device setup features that prevent changes in sensor context from causing a change in exposure when switching between preview/viewfinder and full resolution/snapshot modes. this is achieved by keeping the line rate consistent between modes. exposure defined by the shutter width. this is the number of lines to be reset before starting a frame read. if line rate does not change when a mode changes, exposure does not change. switching from context a to context b under typical/default settings, the sensor pixel rate do ubles when switching from preview (context a) to full resolution (context b). additionally, the number of pixels to be read per line nearly doubles. this naturally keeps the line rates roughly equal. the differ- ence occurs due to border pixels: for soc operation, there are always 8 border pixels regardless of context, thus the number of pixels in each line is not quite doubled. horizontal blanking defined in terms of sensor pixel clocks. the sensor pixel clock rate doubles when switching from low-power readout mode (preview context a) to full-power readout mode (full resolution context b). to mainta in the same horizontal blanking time, the value for horizontal blanking must double. th is is handled by the dual, context-switch- able horizontal blanking registers. f: total frame time: full-power readout: f = (1,032 + 42) x 62.074s = 66,667.556s ? 15 fps (r0x003 + [r0x006 | r00x008]) x (q + a) low-power readout: f = (520 + 17) x 62.074s = 33,333.778s ? 30 fps table 16: user blanking minimum values parameter register minimum horizontal blanking full-power readout (context b): r0 x005 202 (sensor pixel clocks) low-power readout (context a): r0x007 114 (sensor pixel clocks) vertical blanking full-power readout (context b): r0x006 5 (rows) low-power readout (context a): r0x008 5 (rows) table 15: blanking parameter calculations parameter calculation
mt9m131 ds rev. h 5/15 en 53 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing switching modes initiate mode switches from preview (context a) to snapshot (context b) during vertical blanking; switching should be accompanied by a sensor restar t. ensure that r0x0c8[15] is written as ?1? when changing contexts. switching frequency the user can switch between sensor contexts as frequently as necessary (without affecting exposure) constant switches can occur as often as once per frame. simple snapshots to take a snapshot, simply switch from cont ext a to context b (with restart) for a few frames, then switch back again, capturing on e of the context b frames as the snapshot. alternative methods are supported by an inte rnal sequencer. these additional methods are advantageous for ta king flash snapshots. output timing figure 11: vertical timing figure 12: horizontal timing notes: 1. line start: ff00 0080. 2. line end: ff00 009d. line 0 line 1 linen-3 linen-2 linen-1 line 0 frame_valid line_valid d[7:0] ef db c a no data 10 ff 00 00 80 cb0 y0 cr1 y1 cb3 y3 crn -1 yn ff 00 00 9d pixclk line_valid d[7:0] 10
mt9m131: 1/3-inch 1.3mp soc digital image sensor sensor read modes and timing mt9m131 ds rev. h 5/15 en 54 ?semiconductor components industries, llc,2015. typical resolutions, modes, and timing the parameters in table 17 are illustrated in waveform diagram figure 11 on page 53. table 22 on page 57 provides values for these parameters in some common resolutions and operating modes. reset, clocks, and standby functional operation power-up reset is asserted/de-asserted on reset_bar. it is active low. in this reset state, all control registers have the default values. all internal clocks are turned off except for the divided-by-2 clock to the sensor core. soft reset is asserted/de-asserted by the tw o-wire serial interface program. there are sensor core soft resets and soc soft resets. in soft reset mode, the two-wire serial inter- face and register ring bus are still running. all control registers are reset using default values. see r0x00d. hard standby is asserted/de-asserted on standby. it is active high. in this hard standby state, all internal clocks are turned off and analog block is in standby mode to save power consumption. note: following the assertion of hard standby, at least 24 master clock cycles must be deliv- ered to complete the transition to the hard standby state. soft standby is asserted/de-asserted different ly in the sensor page or colorpipe page. the sensor soft standby bit is in r0x00d[2]. colorpipe soft standby disables some of the soc clocks, including the pixel clock. this bit is r0x1b3[0]. the colorpipe must first be brought out of standby through r0x1b3[0]. the colorpipe soft standby is provided to enable the user to turn off the colorpipe and the sensor independently. by default, all outputs except s data are disabled during hard standby. this feature can be disabled by setting r0x1b3[1] = 0. indepe ndent control of the outputs is available either through oe_bar or r0x00d[4]. all outputs are implemented using bidirectional buffers, thus should not be left tri-stated. in dual camera applications, ensure that one camera is driving the bus, or that the bus is pulled to v gnd io or v dd io, even during standby. table 17: blanking definitions designation definition a fv (rising edge) to lv (rising edge) delay b lv (falling edge) to fv (falling edge) delay c lv (high/valid) time d lv (low/horizontal blanking) time e fv (high/valid) time f fv (low/vertical blanking) time
mt9m131 ds rev. h 5/15 en 55 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications electrical specifications note: v dd , v aa , and vaapix must all be at the same potential to avoid excessive current draw. care must be taken to avoid excessive noise injection in th e analog supplies if all three supplies are tied together. table 18: electrical characteristics and operating conditions t a = ambient = 25c parameter condition min typ max unit i/o digital voltage (v dd _io) 1.8 C 3.1 v core digital voltage (v dd ) 2.5 2.8 3.1 v analog voltage (v aa ) 2.5 2.8 3.1 v pixel supply voltage (vaa_pix) 2.5 2.8 3.1 v leakage current standby, no clocks C C 10 a operating temperature measured at junction C30 C +70 c table 19: i/o parameters signal parameter definitions condition min typ max unit all outputs load capacitance C C 30 pf output pin slew 2.8v, 30pf load C 0.72 C v/ns 2.8v, 5pf load C 1.25 C v/ns 1.8v, 30pf load C 0.34 C v/ns 1.8v, 5pf load C 0.51 C v/ns v oh output high voltage v dd io C 0.3 C v dd io v v ol output low voltage 0 C 0.3 v i oh output high current v dd _io = 2.8v, v oh = 2.4v 16 C 26.5 ma v dd _io = 1.8v, v oh = 1.4v 8 C 15 ma i ol output low current v dd _io = 2.8v, v ol = 0.4v 15.9 C 21.3 ma v dd _io = 1.8v, v ol = 0.4v 10.1 C 16.2 ma i oz tri-state output leakage current CC10a all inputs v ih input high voltage v dd io = 2.8v 2.0 C C v v dd io = 1.8v 1.2 C C v v il input low voltage v dd io = 2.8v C C 0.9 v v dd io = 1.8v C C 0.6 v i in input leakage current C5 C +5 a pin cap ball input capacitance C 3.5 C pf extclk freq master clock frequency absolute minimum 2 C C mhz sxga at 15 fps 48 C 54 mhz
mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications mt9m131 ds rev. h 5/15 en 56 ?semiconductor components industries, llc,2015. note: this is a stress rating only, and functional oper ation of the device at these or any other conditions above those indicated in the product specification is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. power consumption caution stresses above those listed in table 20 may cause permanent damage to the device. table 20: absolute maximum ratings symbol parameter rating unit min max v supply power supply voltage (all supplies) C0.3 4.0 v i supply total power supply current 150 ma i gnd total ground current 150 ma v in dc input voltage C0.3 v dd io + 0.3 v v out dc output voltage C0.3 v dd io + 0.3 v t stg storage temperature C40 85 c table 21: power consumption at 2.8v (in mw) mode sensor image flow processor i/os (10pf) total power consumption sxga at 15 fps 90 71 9 170 qsxga at 30 fps 50 36 4 90 qsxga at 15 fps 50 18 2 70 qvga at 30 fps5032183
mt9m131 ds rev. h 5/15 en 57 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications i/o timing by default, the mt9m131 launches pixel data , fv, and lv synchronously with the falling edge of pixclk. this is reflected by the de fault setting of r0x13a [9] and r0x19b[9] = 1. the expectation is that the user captures d out , fv, and lv using the rising edge of pixclk. figure 13: ac output timing diagram notes: 1. measurements for the above table were done at: t a =+25c, v aa = vaa_pix = v dd =v dd _io = 2.8v 2. fv, lv, pixclk ,and d out are referenced from extclk and, therefore, have the same propagation delay with respect to extclk. 3. p = (?) pixclk period table 22: ac output timing data parameters description min typ max unit f extclk input clock frequency C C 54 mhz t extclk_high input clock (extclk) high time 40 50 60 % t extclk_low input clock (extclk) low time 40 50 60 % t rextclk rise time C4.58ns t f extclk fall time C 4.5 8 ns t r dout data out rise time C 4.5 9 ns t f dout data out fall time C 4.5 9 ns t phlp propagation delay from clk high to pixclk low 7 9 15 ns t plhp propagation delay from clk low to pixclk high 7 9 15 ns t pixclk_high pixel clock high time 40 50 60 % t pixclk_low pixel clock low time 40 50 60 % t fvsetup frame valid setup time 4 8 p ns t lvsetup line valid setup time 4 8 p ns t dsetup data out setup time 4 8 p ns t dhold data out hold time 4 8 p ns t phlp t plhp t fvsetup t lvsetup t dsetup t dhold t extclk_high t extclk_low t pixclk _ high t pixclk _ low extclk pixclk fv lv t r t f p [ d out 7:0] d out 7:0] d out [7:0] [
mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications mt9m131 ds rev. h 5/15 en 58 ?semiconductor components industries, llc,2015. 4. minimum and maximum (rise and fall) times for extclk and d out will depend on the type of input signal and load capacitance.
mt9m131 ds rev. h 5/15 en 59 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications figure 14: spectral response chart figure 15: cra versus image height cra versus image height plot image height cra () (%) (mm) 000 5 0.148 1.28 10 0.295 2.56 15 0.443 3.84 20 0.590 5.12 25 0.738 6.40 30 0.885 7.68 35 1.033 8.96 40 1.180 10.25 45 1.328 11.53 50 1.475 12.81 55 1.623 14.09 60 1.770 15.37 65 1.918 16.65 70 2.065 17.93 75 2.213 19.21 80 2.360 20.49 85 2.508 21.77 90 2.656 23.05 95 2.803 24.33 100 2.951 25.61 0 5 10 15 20 25 30 35 40 45 350 450 550 650 750 850 950 1050 wavelength (nm) quantum efficiency (%) cra design 0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 102030405060708090100110 image height (%) cra (deg)
mt9m131: 1/3-inch 1.3mp soc digital image sensor electrical specifications mt9m131 ds rev. h 5/15 en 60 ?semiconductor components industries, llc,2015. figure 16: optical center diagram note: figure not to scale. die center (0 m, 0 m) optical center +15.63 m -37.66 m + direction - direction + direction - direction first clear pixel (26, 8) last clear pixel (1,314, 1,040)
mt9m131 ds rev. h 5/15 en 61 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description appendix a C serial bus description registers are written to and read from the mt9m131 through the two-wire serial inter- face bus. the sensor is a serial interface slave and is controlled by the serial clock (sclk). slck is driven by the serial interface master. data is transferred into and out of the mt9m131 through the serial data (s data ) line. the s data line is pulled up to v dd io off-chip by a 1.5k ? resistor. either the slave or the master device can pull the s data line down?the two-wire serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as shown in the following sequence: 1. astart bit 2. the slave device 8-bit address. the s addr pin is used to select between two different addresses in case of conflict with another device. if s addr is low, the slave address is 0x90; if s addr is high, the slave address is 0xba. 3. an (a no) acknowledge bit 4. an 8-bit message 5. astop bit sequence a typ ical read or write sequence is executed as follows: 1. the master sends a start bit. 2. the master sends the 8-bit slave device addr ess. the last bit of the address determines if the request is a read or a write, where a ?0? indicates a write and a ?1? indicates a read. 3. the slave device acknowledges receipt of the address by sending an acknowledge bit to the master. 4. if the request is a write, the master then transfers the 8-bit register address, indicat- ing where the write takes place. 5. the slave sends an acknowledge bit, indica ting that the register address has been received. 6. the master then transfers the data, 8 bits at a time, with the slave sending an acknowl- edge bit after each 8 bits. the mt9m131 uses 16-bit data for its internal registers, thus requiring two 8-bit trans- fers to write to one register. after 16 bits are transferred, the register address is automati- cally incremented so that the next 16 bits ar e written to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. 1. the master sends the write-mode slave address and 8-bit register address, just as in the write request. 2. the master then sends a start bit and the read-mode slave address, and clocks out the register data, 8 bits at a time. 3. the master sends an acknowledge bit after each 8-bit transfer. the register address is automatically incremented after every 16 bits is transferred. 4. the data transfer is stopped when the master sends a no-acknowledge bit.
mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description mt9m131 ds rev. h 5/15 en 62 ?semiconductor components industries, llc,2015. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interfac e device consists of seven bits of address and 1 bit of direction. a ?0? in the least sign ificant bit (lsb) of the address indicates write mode, and a ?1? indicates read mode. the writ e address of the sensor is 0xba; the read address is 0xbb. this applies only when the s addr is set high. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred 8 bits at a time, foll owed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) rele ases the data line, and the receiver signals an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
mt9m131 ds rev. h 5/15 en 63 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description two-wire serial interface sample write and read sequences (s addr = 1) 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 17. a start bit sent by the master starts the sequence, foll owed by the write address. the image sensor sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor sends an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 17: write timing to r0x009value 0x0284 16-bit read sequence a typical read sequence is shown in figure 18. the master writes the register address, as in a write sequence. then a start bit and th e read address specify that a read is about to occur from the register. the master then cl ocks out the register data, 8 bits at a time. the master sends an acknowledge bit after each 8-bit transfer. the register address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 18: read timing from r0x009; returned value 0x0284 sclk s data 0xba address start stop ack ack ack ack r0x09 0000 0010 1000 0100 sclk s data 0xba address start start stop ack ack ack ack nack r0x09 0xbb address 0000 0010 1000 0100
mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description mt9m131 ds rev. h 5/15 en 64 ?semiconductor components industries, llc,2015. 8-bit write sequence to be able to write one byte at a time to th e register, a special register address is added. the 8-bit write is started by writing the upper 8 bits to the desired register, then writing the lower 8 bits to the special register addres s (r0x0f1). the register is not updated until all 16 bits have been written. it is not possibl e to update just half of a register. figure 19 shows a typical sequence for an 8-bit write. the second byte is written to the special register (r0x0f1). figure 19: write timing to r0x009value 0x0284 8-bit read sequence to read one byte at a time, the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0x0f1), the lower 8 bits are accessed (figure 20). the master sets the no-acknowledge bits. figure 20: read timing from r0x009; returned value 0x0284 sclk s data 0xba address start sto p ack ack ack ack r0x09 0xba address start ack ack r0xf1 0000 0010 1000 0100 sclk s data 0xba address start start ack ack ack nack r0x09 0xbb address 0000 0010 sclk s data 0xba address start start stop ack ack ack nack r0xf1 0xbb address 1000 0100 ? ? ? ?
mt9m131 ds rev. h 5/15 en 65 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the figure 21 and figure 22 in master clock cycles. figure 21: two-wire serial interface ti ming diagram at the pins of the sensor figure 22: two-wire serial interface timi ng diagram at the pins of the sensor (2) sclk s data (sensor receiving data from the master) s data (sensor sending data to the master) t ic t icl t ich t iss t ihd t isd t oaa t isp sclk t ihs t isd t ihp t ihd s data (sensor receiving data from the master)
mt9m131 ds rev. h 5/15 en 66 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor appendix a C serial bus description table 23: two-wire serial interface timing v dd = v aa = vaa_pix= v dd _io = 2.8v, t = C30c to + 70c note: a minimum extclk frequency of 4 mhz is required for the two-wire serial interface to operate at 400 khz. symbol definition min typ max unit f ic two-wire serial bus input clock frequency C C 400 khz t ic two-wire serial bus input clock period 2500 C C ns t icl two-wire serial bus clock low C 1250 C ns t ich two-wire serial bus clock high C 1250 C ns t iss setup time for start condition 600 C C ns t ihs hold time for start condition 600 C C ns t isd setup time for input data 600 C C ns t ihd hold time for input data 600 C C ns t oaa output delay time C C 600 ns t isp setup time of stop condit j on 600 C C ns t ihp hold time for stop condition 600 C C ns c s clck /s data sclck and s data load capacitance C C 30 pf r s clck /s data sclck and s data pull-up resistor C 1.5 C k ?
mt9m131 ds rev. h 5/15 en 67 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor package dimensions package dimensions the mt9m131 comes in a 48-pin clcc package, shown in figure 23. figure 23: 48-pin clcc package notes: 1. an ir-cut filter is required to obtain optimal image quality. 2. all dimensions are in millimeters. seating plane 4.4 11.43 5.215 5.715 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 0.7 thickness 8.8 4.4 5.715 4.84 5.215 0.8 typ 1.75 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1.0 0.2 48x r 0.15 48x 0.40 0.05 11.43 10.9 0.1 ctr lead finish: au plating, 0.50 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.3 0.2 1.7 note: 1. optical center = package center. first clear pixel optical center 1 c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 100 microns a d 0.90 for reference only 1.400 0.125 0.35 for reference only v ctr ?0.20 a b c h ctr ?0.20 a b c image sensor die: 0.675 thickness 0.10 a 0.05 0.2 4x
mt9m131 ds rev. h 5/15 en 68 ?semiconductor components industries, llc,2015. mt9m131: 1/3-inch 1.3mp soc digital image sensor revision history revision history rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/13/15 ? updated ?ordering information? on page 2 rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/27/15 ? converted to on semiconductor template rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/3/11 ? updated trademarks ? applied updated template rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/4/10 ? updated to non-confidential rev d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/23/10 ? updated to aptina template ? deleted all mention of 44-pin icsp pack age as this is no longer available ? removed es designation from 48-pin clcc package part numbers rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/1/2008 ? updated registers from decimal to hex format ? updated figure 14: ?spectral response chart,? on page 59 ? added figure 15: ?cra versus image height,? on page 59 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 03/02/2007 ? updated "features" on page 1 ? updated table 1, ?key performance parameters,? on page 1 ? added table 2, ?available part numbers,? on page 1 ? updated "general description" on page 6 ? updated "functional overview" on page 7 ? updated figure 1: ?functional block diagram,? on page 7 ? updated "internal architecture" on page 8 ? updated figure 2: ?internal registers grouping,? on page 8 ? updated "register operations" on page 9 ? updated figure 4: ?typical conf iguration (connection),? on page 10 ? updated "pin/ball assignment" on page 11 ? updated figure 5: ?48-pin clcc assignment,? on page 11 ? updated figure 6: ?sensor core block diagram,? on page 36 ? updated "itu-r bt.656 and rgb output" on page 12 ? updated "configuration" on page 21 ? updated "camera control registers" on page 30 ? updated "i/o timing" on page 57 ? updated figure 14: ?spectral response chart,? on page 59 ? updated table 22, ?ac output timing data,? on page 57 ? updated figure 23: ?48-pin clcc package,? on page 67
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9m131: 1/3-inch 1.3mp soc digital image sensor revision history mt9m131 ds rev. h 5/15 en 69 ?semiconductor components industries, llc,2015 . rev. a, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/11/06 ?initial release

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